From 9faabdd5ddc6d57873a0edcfbaee85e8d4b5d5ac Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Sat, 30 Mar 2024 23:45:15 +0100 Subject: [PATCH] ac/nir/tess: Remove superfluous args for reserved TCS outputs. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Timur Kristóf Reviewed-by: Marek Olšák Part-of: --- src/amd/common/ac_nir.h | 2 -- src/amd/common/ac_nir_lower_tess_io_to_mem.c | 2 -- src/amd/vulkan/nir/radv_nir_lower_io.c | 3 +-- src/gallium/drivers/radeonsi/si_shader.c | 2 -- 4 files changed, 1 insertion(+), 8 deletions(-) diff --git a/src/amd/common/ac_nir.h b/src/amd/common/ac_nir.h index eebb2e37fb9..0968bb5b80f 100644 --- a/src/amd/common/ac_nir.h +++ b/src/amd/common/ac_nir.h @@ -132,8 +132,6 @@ ac_nir_lower_hs_outputs_to_mem(nir_shader *shader, enum amd_gfx_level gfx_level, uint64_t tes_inputs_read, uint32_t tes_patch_inputs_read, - unsigned num_reserved_tcs_outputs, - unsigned num_reserved_tcs_patch_outputs, unsigned wave_size, bool no_inputs_in_lds, bool pass_tessfactors_by_reg); diff --git a/src/amd/common/ac_nir_lower_tess_io_to_mem.c b/src/amd/common/ac_nir_lower_tess_io_to_mem.c index 4043a56f4f7..393f8238b20 100644 --- a/src/amd/common/ac_nir_lower_tess_io_to_mem.c +++ b/src/amd/common/ac_nir_lower_tess_io_to_mem.c @@ -947,8 +947,6 @@ ac_nir_lower_hs_outputs_to_mem(nir_shader *shader, enum amd_gfx_level gfx_level, uint64_t tes_inputs_read, uint32_t tes_patch_inputs_read, - unsigned num_reserved_tcs_outputs, - unsigned num_reserved_tcs_patch_outputs, unsigned wave_size, bool no_inputs_in_lds, bool pass_tessfactors_by_reg) diff --git a/src/amd/vulkan/nir/radv_nir_lower_io.c b/src/amd/vulkan/nir/radv_nir_lower_io.c index 80d491d9525..b8cae01926b 100644 --- a/src/amd/vulkan/nir/radv_nir_lower_io.c +++ b/src/amd/vulkan/nir/radv_nir_lower_io.c @@ -154,8 +154,7 @@ radv_nir_lower_io_to_mem(struct radv_device *device, struct radv_shader_stage *s } else if (nir->info.stage == MESA_SHADER_TESS_CTRL) { NIR_PASS_V(nir, ac_nir_lower_hs_inputs_to_mem, map_input, info->vs.tcs_in_out_eq); NIR_PASS_V(nir, ac_nir_lower_hs_outputs_to_mem, map_output, pdev->info.gfx_level, info->tcs.tes_inputs_read, - info->tcs.tes_patch_inputs_read, info->tcs.num_linked_outputs, info->tcs.num_linked_patch_outputs, - info->wave_size, false, false); + info->tcs.tes_patch_inputs_read, info->wave_size, false, false); return true; } else if (nir->info.stage == MESA_SHADER_TESS_EVAL) { diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index f01487ec271..619b06a00d4 100644 --- a/src/gallium/drivers/radeonsi/si_shader.c +++ b/src/gallium/drivers/radeonsi/si_shader.c @@ -1795,8 +1795,6 @@ static bool si_lower_io_to_mem(struct si_shader *shader, nir_shader *nir, NIR_PASS_V(nir, ac_nir_lower_hs_outputs_to_mem, si_map_io_driver_location, sel->screen->info.gfx_level, ~0ULL, ~0U, /* no TES inputs filter */ - util_last_bit64(sel->info.outputs_written_before_tes_gs), - util_last_bit64(sel->info.patch_outputs_written), shader->wave_size, /* ALL TCS inputs are passed by register. */ key->ge.opt.same_patch_vertices &&