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radv: remove radv_get_image_cmask_info()

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It's unnecessary to duplicate fields in another struct.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Samuel Pitoiset 2019-08-01 17:59:55 +02:00
parent 856487a280
commit 9c9745e8dd
4 changed files with 21 additions and 45 deletions
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4
src/amd/vulkan/radv_device.c
View file

@ -4408,7 +4408,7 @@ radv_initialise_color_surface(struct radv_device *device,
cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
cb->cb_color_cmask_slice = surf->u.legacy.cmask_slice_tile_max;
cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
@ -4428,7 +4428,7 @@ radv_initialise_color_surface(struct radv_device *device,
/* CMASK variables */
va = radv_buffer_get_va(iview->bo) + iview->image->offset;
va += iview->image->cmask.offset;
va += iview->image->cmask_offset;
cb->cb_color_cmask = va >> 8;
va = radv_buffer_get_va(iview->bo) + iview->image->offset;

38
src/amd/vulkan/radv_image.c
View file

@ -937,7 +937,7 @@ si_make_texture_descriptor(struct radv_device *device,
S_008F24_META_RB_ALIGNED(image->planes[0].surface.u.gfx9.cmask.rb_aligned);
if (radv_image_is_tc_compat_cmask(image)) {
va = gpu_address + image->offset + image->cmask.offset;
va = gpu_address + image->offset + image->cmask_offset;
fmask_state[5] |= S_008F24_META_DATA_ADDRESS(va >> 40);
fmask_state[6] |= S_008F28_COMPRESSION_EN(1);
@ -950,7 +950,7 @@ si_make_texture_descriptor(struct radv_device *device,
fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
if (radv_image_is_tc_compat_cmask(image)) {
va = gpu_address + image->offset + image->cmask.offset;
va = gpu_address + image->offset + image->cmask_offset;
fmask_state[6] |= S_008F28_COMPRESSION_EN(1);
fmask_state[7] |= va >> 8;
@ -1136,45 +1136,27 @@ radv_image_alloc_fmask(struct radv_device *device,
image->alignment = MAX2(image->alignment, image->fmask.alignment);
}
static void
radv_image_get_cmask_info(struct radv_device *device,
struct radv_image *image,
struct radv_cmask_info *out)
{
assert(image->plane_count == 1);
if (device->physical_device->rad_info.chip_class >= GFX9) {
out->alignment = image->planes[0].surface.cmask_alignment;
out->size = image->planes[0].surface.cmask_size;
return;
}
out->slice_tile_max = image->planes[0].surface.u.legacy.cmask_slice_tile_max;
out->alignment = image->planes[0].surface.cmask_alignment;
out->slice_size = image->planes[0].surface.cmask_slice_size;
out->size = image->planes[0].surface.cmask_size;
}
static void
radv_image_alloc_cmask(struct radv_device *device,
struct radv_image *image)
{
unsigned cmask_alignment = image->planes[0].surface.cmask_alignment;
unsigned cmask_size = image->planes[0].surface.cmask_size;
uint32_t clear_value_size = 0;
radv_image_get_cmask_info(device, image, &image->cmask);
if (!image->cmask.size)
if (!cmask_size)
return;
assert(image->cmask.alignment);
assert(cmask_alignment);
image->cmask.offset = align64(image->size, image->cmask.alignment);
image->cmask_offset = align64(image->size, cmask_alignment);
/* + 8 for storing the clear values */
if (!image->clear_value_offset) {
image->clear_value_offset = image->cmask.offset + image->cmask.size;
image->clear_value_offset = image->cmask_offset + cmask_size;
clear_value_size = 8;
}
image->size = image->cmask.offset + image->cmask.size + clear_value_size;
image->alignment = MAX2(image->alignment, image->cmask.alignment);
image->size = image->cmask_offset + cmask_size + clear_value_size;
image->alignment = MAX2(image->alignment, cmask_alignment);
}
static void

11
src/amd/vulkan/radv_meta_clear.c
View file

@ -1330,15 +1330,18 @@ radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image,
const VkImageSubresourceRange *range, uint32_t value)
{
uint64_t offset = image->offset + image->cmask.offset;
uint64_t offset = image->offset + image->cmask_offset;
uint64_t size;
if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
/* TODO: clear layers. */
size = image->cmask.size;
size = image->planes[0].surface.cmask_size;
} else {
offset += image->cmask.slice_size * range->baseArrayLayer;
size = image->cmask.slice_size * radv_get_layerCount(image, range);
unsigned cmask_slice_size =
image->planes[0].surface.cmask_slice_size;
offset += cmask_slice_size * range->baseArrayLayer;
size = cmask_slice_size * radv_get_layerCount(image, range);
}
return radv_fill_buffer(cmd_buffer, image->bo, offset, size, value);

13
src/amd/vulkan/radv_private.h
View file

@ -1561,15 +1561,6 @@ struct radv_fmask_info {
uint64_t slice_size;
};
struct radv_cmask_info {
uint64_t offset;
uint64_t size;
unsigned alignment;
unsigned slice_tile_max;
unsigned slice_size;
};
struct radv_image_plane {
VkFormat format;
struct radeon_surf surface;
@ -1604,7 +1595,7 @@ struct radv_image {
bool tc_compatible_cmask;
struct radv_fmask_info fmask;
struct radv_cmask_info cmask;
uint64_t cmask_offset;
uint64_t clear_value_offset;
uint64_t fce_pred_offset;
uint64_t dcc_pred_offset;
@ -1654,7 +1645,7 @@ bool radv_layout_dcc_compressed(const struct radv_image *image,
static inline bool
radv_image_has_cmask(const struct radv_image *image)
{
return image->cmask.size;
return image->planes[0].surface.cmask_size;
}
/**