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radv: only account for tile_swizzle for color surfaces with DCC

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It's 0 for depth surfaces with TC compat HTILE enabled.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Samuel Pitoiset 2019-08-01 15:45:10 +02:00
parent e1c5d8a364
commit 856487a280
1 changed files with 3 additions and 3 deletions
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6
src/amd/vulkan/radv_image.c
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@ -483,6 +483,8 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
meta_va = gpu_address + image->dcc_offset;
if (chip_class <= GFX8)
meta_va += base_level_info->dcc_offset;
meta_va |= (uint32_t)plane->surface.tile_swizzle << 8;
} else if (!is_storage_image &&
radv_image_is_tc_compat_htile(image)) {
meta_va = gpu_address + image->htile_offset;
@ -490,10 +492,8 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
if (meta_va) {
state[6] |= S_008F28_COMPRESSION_EN(1);
if (chip_class <= GFX9) {
if (chip_class <= GFX9)
state[7] = meta_va >> 8;
state[7] |= plane->surface.tile_swizzle;
}
}
}