From 9baa57158de95104c5980a7546ab59f5552b50ae Mon Sep 17 00:00:00 2001
From: Rohan Garg <rohan.garg@intel.com>
Date: Wed, 6 Mar 2024 14:27:56 +0100
Subject: [PATCH] intel/genxml: update PIPE_CONTROL so that we can decode it on
 the CCS

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28013>
---
 src/intel/genxml/gen20.xml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/genxml/gen20.xml b/src/intel/genxml/gen20.xml
index 315f6a9ecfa..addc078470a 100644
--- a/src/intel/genxml/gen20.xml
+++ b/src/intel/genxml/gen20.xml
@@ -813,7 +813,7 @@
     <field name="Command SubType" start="27" end="28" type="uint" default="1" />
     <field name="Command Type" start="29" end="31" type="uint" default="3" />
   </instruction>
-  <instruction name="PIPE_CONTROL" bias="2" length="6" engine="render">
+  <instruction name="PIPE_CONTROL" bias="2" length="6" engine="render|compute">
     <field name="DWord Length" start="0" end="7" type="uint" default="4" />
     <field name="HDC Pipeline Flush Enable" start="9" end="9" type="bool" />
     <field name="L3 Read Only Cache Invalidation Enable" start="10" end="10" type="bool" />