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asahi: don't allocate tib space for gaps

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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28483>
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Alyssa Rosenzweig 2024-03-18 14:58:03 -04:00 • committed by Marge Bot
parent eadf4cfe1c
commit 99a4d0fcad
1 changed files with 6 additions and 0 deletions
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6
src/asahi/lib/agx_tilebuffer.c
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@ -60,6 +60,12 @@ agx_build_tilebuffer_layout(const enum pipe_format *formats, uint8_t nr_cbufs,
for (unsigned rt = 0; rt < nr_cbufs; ++rt) {
tib.logical_format[rt] = formats[rt];
/* If there are gaps in the layout, don't allocate holes. Obscure,
* PIPE_FORMAT_NONE has a size of 1, not 0.
*/
if (formats[rt] == PIPE_FORMAT_NONE)
continue;
/* Require natural alignment for tilebuffer allocations. This could be
* optimized, but this shouldn't be a problem in practice.
*/