From 992e9d07c5519fc86fe7915de35b2281920afcfd Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Sun, 26 Jan 2025 21:50:06 +0100 Subject: [PATCH] etnaviv: drm: fix instruction limit for cores with instruction cache Some cores with the the instruction cache feature, such as the GC3000 found on the i.MX6QP, have a wrong instruction limit encoded in hardware. The HWDB entry for this core has the correct number (512). Fixup all cores with the instruction cache feature to report at least 512 instructions, which was already assumed when configuring the VS/FS instruction state memory split in other parts of the driver. Signed-off-by: Lucas Stach Reviewed-by: Christian Gmeiner Part-of: --- src/etnaviv/drm/etnaviv_gpu.c | 8 ++++++++ src/gallium/drivers/etnaviv/etnaviv_screen.c | 6 ++---- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/src/etnaviv/drm/etnaviv_gpu.c b/src/etnaviv/drm/etnaviv_gpu.c index a3bf6574df8..11739257519 100644 --- a/src/etnaviv/drm/etnaviv_gpu.c +++ b/src/etnaviv/drm/etnaviv_gpu.c @@ -259,6 +259,14 @@ struct etna_gpu *etna_gpu_new(struct etna_device *dev, unsigned int core) if (!core_info_okay) { query_features_from_kernel(gpu); query_limits_from_kernel(gpu); + + /* GC3000 with the instruction cache feature has a incorrect instruction + * limit encoded in HW (HWDB has the correct number). Fix this up so + * other parts of the stack don't have to worry about this. + */ + if (etna_core_has_feature(&gpu->info, ETNA_FEATURE_INSTRUCTION_CACHE) && + gpu->info.gpu.max_instructions < 512) + gpu->info.gpu.max_instructions = 512; } determine_halti(gpu); diff --git a/src/gallium/drivers/etnaviv/etnaviv_screen.c b/src/gallium/drivers/etnaviv/etnaviv_screen.c index 46a4851e38e..5f0c33a9a21 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_screen.c +++ b/src/gallium/drivers/etnaviv/etnaviv_screen.c @@ -870,10 +870,8 @@ etna_get_specs(struct etna_screen *screen) screen->specs.has_icache = true; } else if (VIV_FEATURE(screen, ETNA_FEATURE_INSTRUCTION_CACHE)) { /* GC3000 - this core is capable of loading shaders from - * memory. It can also run shaders from registers, as a fallback, but - * "max_instructions" does not have the correct value. It has place for - * 2*256 instructions just like GC2000, but the offsets are slightly - * different. + * memory. It can also run shaders from registers as a fallback, but the + * offsets are slightly different. */ screen->specs.vs_offset = 0xC000; /* State 08000-0C000 mirrors 0C000-0E000, and the Vivante driver uses