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pan/va/disasm: Align indentation
The disassembly file had a lot of inconsitencies in indentation, so align on the standard IndentWidth: 3 Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com> Reviewed-by: Eric R. Smith <eric.smith@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41062>
This commit is contained in:
Lars-Ivar Hesselberg Simonsen
Marge Bot
parent
17f1a2c184
commit
98c298cf4d
1 changed files with 124 additions and 125 deletions
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@ -31,64 +31,64 @@ template = """
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% for name, en in ENUMS.items():
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UNUSED static const char *valhall_${name}[] = {
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% for v in en.values:
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"${"" if v.default else "." + v.value}",
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"${"" if v.default else "." + v.value}",
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% endfor
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};
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% endfor
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static const uint32_t va_immediates[32] = {
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% for imm in IMMEDIATES:
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${hex(imm)},
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${hex(imm)},
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% endfor
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};
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static inline void
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va_print_src(FILE *fp, unsigned type, unsigned value, unsigned size, unsigned fau_page)
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{
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if (type == VA_SRC_IMM_TYPE) {
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if (value >= 32) {
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if (fau_page == 0)
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fputs(valhall_fau_special_page_0[(value - 0x20) >> 1] + 1, fp);
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else if (fau_page == 1)
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fputs(valhall_fau_special_page_1[(value - 0x20) >> 1] + 1, fp);
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else if (fau_page == 3)
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fputs(valhall_fau_special_page_3[(value - 0x20) >> 1] + 1, fp);
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else
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fprintf(fp, "reserved_page2");
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if (type == VA_SRC_IMM_TYPE) {
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if (value >= 32) {
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if (fau_page == 0)
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fputs(valhall_fau_special_page_0[(value - 0x20) >> 1] + 1, fp);
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else if (fau_page == 1)
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fputs(valhall_fau_special_page_1[(value - 0x20) >> 1] + 1, fp);
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else if (fau_page == 3)
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fputs(valhall_fau_special_page_3[(value - 0x20) >> 1] + 1, fp);
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else
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fprintf(fp, "reserved_page2");
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fprintf(fp, ".w%u", value & 1);
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} else {
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fprintf(fp, "0x%X", va_immediates[value]);
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}
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} else if (type == VA_SRC_UNIFORM_TYPE) {
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fprintf(fp, "u%u", value >> 1 | (fau_page << 5));
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if (size <= 32)
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fprintf(fp, ".w%u", value & 1);
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} else {
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bool discard = (type & 1);
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char *dmark = discard ? "^" : "";
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if (size > 32)
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fprintf(fp, "[r%u%s:r%u%s]", value, dmark, value + 1, dmark);
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else
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fprintf(fp, "r%u%s", value, dmark);
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}
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fprintf(fp, ".w%u", value & 1);
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} else {
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fprintf(fp, "0x%X", va_immediates[value]);
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}
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} else if (type == VA_SRC_UNIFORM_TYPE) {
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fprintf(fp, "u%u", value >> 1 | (fau_page << 5));
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if (size <= 32)
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fprintf(fp, ".w%u", value & 1);
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} else {
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bool discard = (type & 1);
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char *dmark = discard ? "^" : "";
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if (size > 32)
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fprintf(fp, "[r%u%s:r%u%s]", value, dmark, value + 1, dmark);
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else
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fprintf(fp, "r%u%s", value, dmark);
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}
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}
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static inline void
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va_print_float_src(FILE *fp, unsigned type, unsigned value, unsigned size, unsigned fau_page, bool neg, bool abs)
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{
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if (type == VA_SRC_IMM_TYPE) {
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assert(value < 32 && "overflow in LUT");
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fprintf(fp, "0x%X", va_immediates[value]);
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} else {
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va_print_src(fp, type, value, size, fau_page);
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}
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if (type == VA_SRC_IMM_TYPE) {
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assert(value < 32 && "overflow in LUT");
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fprintf(fp, "0x%X", va_immediates[value]);
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} else {
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va_print_src(fp, type, value, size, fau_page);
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}
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if (neg)
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fprintf(fp, ".neg");
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if (neg)
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fprintf(fp, ".neg");
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if (abs)
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fprintf(fp, ".abs");
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if (abs)
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fprintf(fp, ".abs");
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}
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static inline void
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@ -105,91 +105,90 @@ va_print_dest(FILE *fp, unsigned mask, unsigned value, unsigned size)
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<%def name="print_instr(op)">
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<% no_comma = True %>
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fputs("${op.name}", fp);
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fputs("${op.name}", fp);
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% for mod in op.modifiers:
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% if mod.name not in ["staging_register_count", "staging_register_write_count"]:
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% if mod.is_enum:
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fputs(valhall_${safe_name(mod.enum)}[(instr >> ${mod.start}) & ${hex((1 << mod.size) - 1)}], fp);
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fputs(valhall_${safe_name(mod.enum)}[(instr >> ${mod.start}) & ${hex((1 << mod.size) - 1)}], fp);
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% else:
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if (instr & BIT(${mod.start})) fputs(".${mod.name}", fp);
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if (instr & BIT(${mod.start})) fputs(".${mod.name}", fp);
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% endif
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% endif
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% endfor
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fprintf(fp, "%s ", valhall_flow[(instr >> ${op.offset['flow']}) & ${hex(op.mask['flow'])}]);
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fprintf(fp, "%s ", valhall_flow[(instr >> ${op.offset['flow']}) & ${hex(op.mask['flow'])}]);
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% for i, dest in enumerate(op.dests):
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<% no_comma = False %>
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va_print_dest(fp, (instr >> ${dest.offset['mode']}) & ${hex(dest.mask['mode'])}, (instr >> ${dest.offset['value']}) & ${hex(dest.mask['value'])}, ${dest.size});
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va_print_dest(fp, (instr >> ${dest.offset['mode']}) & ${hex(dest.mask['mode'])}, (instr >> ${dest.offset['value']}) & ${hex(dest.mask['value'])}, ${dest.size});
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% endfor
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% for index, sr in enumerate(op.staging):
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% if not no_comma:
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fputs(", ", fp);
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fputs(", ", fp);
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% endif
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<%
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no_comma = False
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no_comma = False
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if sr.count != 0:
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sr_count = sr.count;
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else:
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for mod in op.modifiers:
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if mod.name == "staging_register_write_count" and sr.write:
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sr_count = f"(((instr >> {mod.start}) & {hex((1 << mod.size) - 1)}) + 1)";
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elif mod.name == "staging_register_count":
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sr_count = f"((instr >> {mod.start}) & {hex((1 << mod.size) - 1)})";
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if sr.count != 0:
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sr_count = sr.count;
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else:
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for mod in op.modifiers:
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if mod.name == "staging_register_write_count" and sr.write:
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sr_count = f"(((instr >> {mod.start}) & {hex((1 << mod.size) - 1)}) + 1)";
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elif mod.name == "staging_register_count":
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sr_count = f"((instr >> {mod.start}) & {hex((1 << mod.size) - 1)})";
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%>
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// assert(((instr >> ${sr.start}) & 0xC0) == ${sr.encoded_flags});
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fprintf(fp, "@");
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for (unsigned i = 0; i < ${sr_count}; ++i) {
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fprintf(fp, "%sr%u", (i == 0) ? "" : ":",
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(uint32_t) (((instr >> ${sr.offset['value']}) & ${hex(sr.mask['value'])}) + i));
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}
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// assert(((instr >> ${sr.start}) & 0xC0) == ${sr.encoded_flags});
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fprintf(fp, "@");
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for (unsigned i = 0; i < ${sr_count}; ++i) {
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fprintf(fp, "%sr%u", (i == 0) ? "" : ":",
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(uint32_t) (((instr >> ${sr.offset['value']}) & ${hex(sr.mask['value'])}) + i));
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}
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% endfor
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% for i, src in enumerate(op.srcs):
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% if not no_comma:
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fputs(", ", fp);
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fputs(", ", fp);
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% endif
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<% no_comma = False %>
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% if src.absneg:
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va_print_float_src(fp, (instr >> ${src.offset['mode']}) & ${hex(src.mask['mode'])}, (instr >> ${src.offset['value']}) & ${hex(src.mask['value'])},
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${src.size}, (instr >> ${op.offset['fau_page']}) & ${hex(op.mask['fau_page'])},
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instr & BIT(${src.offset['neg']}),
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instr & BIT(${src.offset['abs']}));
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va_print_float_src(fp, (instr >> ${src.offset['mode']}) & ${hex(src.mask['mode'])}, (instr >> ${src.offset['value']}) & ${hex(src.mask['value'])},
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${src.size}, (instr >> ${op.offset['fau_page']}) & ${hex(op.mask['fau_page'])},
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instr & BIT(${src.offset['neg']}),
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instr & BIT(${src.offset['abs']}));
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% elif src.is_float:
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va_print_float_src(fp, (instr >> ${src.offset['mode']}) & ${src.mask['mode']}, (instr >> ${src.offset['value']}) & ${hex(src.mask['value'])},
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${src.size}, (instr >> ${op.offset['fau_page']}) & ${hex(op.mask['fau_page'])}, false, false);
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va_print_float_src(fp, (instr >> ${src.offset['mode']}) & ${src.mask['mode']}, (instr >> ${src.offset['value']}) & ${hex(src.mask['value'])},
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${src.size}, (instr >> ${op.offset['fau_page']}) & ${hex(op.mask['fau_page'])}, false, false);
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% else:
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va_print_src(fp, (instr >> ${src.offset['mode']}) & ${src.mask['mode']}, (instr >> ${src.offset['value']}) & ${hex(src.mask['value'])},
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${src.size}, (instr >> ${op.offset['fau_page']}) & ${hex(op.mask['fau_page'])});
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va_print_src(fp, (instr >> ${src.offset['mode']}) & ${src.mask['mode']}, (instr >> ${src.offset['value']}) & ${hex(src.mask['value'])},
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${src.size}, (instr >> ${op.offset['fau_page']}) & ${hex(op.mask['fau_page'])});
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% endif
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% if src.swizzle:
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% if src.size == 32:
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fputs(valhall_widen[(instr >> ${src.offset['swizzle']}) & ${hex(src.mask['swizzle'])}], fp);
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fputs(valhall_widen[(instr >> ${src.offset['swizzle']}) & ${hex(src.mask['swizzle'])}], fp);
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% else:
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fputs(valhall_swizzles_16_bit[(instr >> ${src.offset['swizzle']}) & ${hex(src.mask['swizzle'])}], fp);
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fputs(valhall_swizzles_16_bit[(instr >> ${src.offset['swizzle']}) & ${hex(src.mask['swizzle'])}], fp);
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% endif
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% endif
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% if src.lanes:
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fputs(valhall_lanes_8_bit[(instr >> ${src.offset['widen']}) & ${hex(src.mask['widen'])}], fp);
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fputs(valhall_lanes_8_bit[(instr >> ${src.offset['widen']}) & ${hex(src.mask['widen'])}], fp);
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% elif src.halfswizzle:
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fputs(valhall_half_swizzles_8_bit[(instr >> ${src.offset['widen']}) & ${hex(src.mask['widen'])}], fp);
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fputs(valhall_half_swizzles_8_bit[(instr >> ${src.offset['widen']}) & ${hex(src.mask['widen'])}], fp);
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% elif src.widen:
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fputs(valhall_swizzles_${src.size}_bit[(instr >> ${src.offset['widen']}) & ${hex(src.mask['widen'])}], fp);
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fputs(valhall_swizzles_${src.size}_bit[(instr >> ${src.offset['widen']}) & ${hex(src.mask['widen'])}], fp);
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% elif src.combine:
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fputs(valhall_combine[(instr >> ${src.offset['combine']}) & ${hex(src.mask['combine'])}], fp);
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fputs(valhall_combine[(instr >> ${src.offset['combine']}) & ${hex(src.mask['combine'])}], fp);
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% endif
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% if src.lane:
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fputs(valhall_lane_${src.size}_bit[(instr >> ${src.offset['lane']}) & ${hex(src.mask['lane'])}], fp);
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fputs(valhall_lane_${src.size}_bit[(instr >> ${src.offset['lane']}) & ${hex(src.mask['lane'])}], fp);
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% endif
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% if 'not' in src.offset:
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if (instr & BIT(${src.offset['not']})) fputs(".not", fp);
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if (instr & BIT(${src.offset['not']})) fputs(".not", fp);
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% endif
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% endfor
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% for imm in op.immediates:
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<%
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prefix = "#" if imm.name == "constant" else imm.name + ":"
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fmt = "%d" if imm.signed else "0x%X"
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prefix = "#" if imm.name == "constant" else imm.name + ":"
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fmt = "%d" if imm.signed else "0x%X"
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%>
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fprintf(fp, ", ${prefix}${fmt}", (uint32_t) ${"SEXT(" if imm.signed else ""}
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((instr >> ${imm.start}) & MASK(${imm.size})) ${f", {imm.size})" if imm.signed else ""});
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fprintf(fp, ", ${prefix}${fmt}", (uint32_t) ${"SEXT(" if imm.signed else ""} ((instr >> ${imm.start}) & MASK(${imm.size})) ${f", {imm.size})" if imm.signed else ""});
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% endfor
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</%def>
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@ -197,16 +196,16 @@ va_print_dest(FILE *fp, unsigned mask, unsigned value, unsigned size)
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%if op_bucket.instr:
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${print_instr(op_bucket.instr)}
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%else:
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opcode = (instr >> ${op_bucket.start}) & ${hex(op_bucket.mask)};
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switch (opcode) {
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opcode = (instr >> ${op_bucket.start}) & ${hex(op_bucket.mask)};
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switch (opcode) {
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%for op in op_bucket.children:
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case ${hex(op)}:
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{
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case ${hex(op)}:
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{
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${recurse_subcodes(op_bucket.children[op])}
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break;
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}
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break;
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}
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%endfor
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}
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}
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%endif
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</%def>
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@ -222,12 +221,12 @@ ${recurse_subcodes(OPCODES)}
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static bool is_branch(uint64_t instr)
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{
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<% (exact, mask) = OPCODES.get_exact_mask("BRANCHZ") %>
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if ((instr & ${hex(mask)}) == ${hex(exact)})
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return true;
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if ((instr & ${hex(mask)}) == ${hex(exact)})
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return true;
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<% (exact, mask) = OPCODES.get_exact_mask("BRANCHZI") %>
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if ((instr & ${hex(mask)}) == ${hex(exact)})
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return true;
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return false;
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if ((instr & ${hex(mask)}) == ${hex(exact)})
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return true;
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return false;
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}
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void
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@ -270,46 +269,46 @@ disassemble_valhall(FILE *fp, const void *code, size_t size, bool verbose)
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"""
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class OpBucket:
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def __init__(self):
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self.start = None
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self.mask = None
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self.instr = None
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self.children = {}
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def __init__(self):
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self.start = None
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self.mask = None
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self.instr = None
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self.children = {}
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def insert(self, subcodes, ins):
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if len(subcodes) == 0:
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self.instr = ins
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else:
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sc = subcodes[0]
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assert(self.start is None or self.start == sc.start)
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assert(self.mask is None or self.mask == sc.mask)
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self.start = sc.start
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self.mask = sc.mask
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if sc.value not in self.children:
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self.children[sc.value] = OpBucket()
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self.children[sc.value].insert(subcodes[1:], ins)
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def insert(self, subcodes, ins):
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if len(subcodes) == 0:
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self.instr = ins
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else:
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sc = subcodes[0]
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assert(self.start is None or self.start == sc.start)
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assert(self.mask is None or self.mask == sc.mask)
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self.start = sc.start
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self.mask = sc.mask
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if sc.value not in self.children:
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self.children[sc.value] = OpBucket()
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self.children[sc.value].insert(subcodes[1:], ins)
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def get_exact_mask(self, op_name, exact = 0, mask = 0):
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if self.instr:
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if self.instr.name == op_name:
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return (exact, mask)
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else:
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return ()
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else:
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for op in self.children:
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exact_mask = self.children[op].get_exact_mask(op_name,
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exact | (op << self.start),
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mask | (self.mask << self.start))
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if exact_mask:
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return exact_mask
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def get_exact_mask(self, op_name, exact = 0, mask = 0):
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if self.instr:
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if self.instr.name == op_name:
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return (exact, mask)
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else:
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return ()
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else:
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for op in self.children:
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exact_mask = self.children[op].get_exact_mask(op_name,
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exact | (op << self.start),
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mask | (self.mask << self.start))
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if exact_mask:
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return exact_mask
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return ()
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# Build opcode hierarchy:
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OPCODES = OpBucket()
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for ins in instructions:
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OPCODES.insert(ins.opcode, ins)
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OPCODES.insert(ins.opcode, ins)
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try:
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print(Template(template).render(OPCODES = OPCODES, IMMEDIATES = immediates, ENUMS = enums, typesize = typesize, safe_name = safe_name))
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print(Template(template).render(OPCODES = OPCODES, IMMEDIATES = immediates, ENUMS = enums, typesize = typesize, safe_name = safe_name))
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except:
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print(exceptions.text_error_template().render())
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print(exceptions.text_error_template().render())
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