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pan/va/disasm: Align FAU printing
The current implementation prints FAU entries as 32-bit entries. While this works, it does not align with the DDK. Rather than treating FAU as a set of 32-bit entries, treat is as 64-bit entries that can be split in two words. This aligns with the DDK and has allows for differentiating 32-bit and 64-bit reads based on whether a word modifier is used. Finally, add entry values to FAU printing to easily look up specific reads. For example: Vertex FAU @ffd93950: 43000000 43000000 3F800000 43000000 43000000 00000000 C7000000 47000000 00000001 00000000 FMAX.f32 r3, r3^, u6 FMIN.f32 r3, r3^, u7 vs Vertex FAU @ffd93950: u0 43000000 43000000 u1 3F800000 43000000 u2 43000000 00000000 u3 C7000000 47000000 u4 00000001 00000000 FMAX.f32 r3, r3^, u3.w0 FMIN.f32 r3, r3^, u3.w1 Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com> Reviewed-by: Eric R. Smith <eric.smith@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41062>
This commit is contained in:
Lars-Ivar Hesselberg Simonsen
Marge Bot
parent
829eafa076
commit
17f1a2c184
4 changed files with 39 additions and 34 deletions
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@ -99,8 +99,8 @@ def encode_source(op, fau):
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return parse_int(op[1:], 0, 63)
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elif op[0] == 'u':
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val = parse_int(op[1:], 0, 127)
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fau.set_page(val >> 6)
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return (val & 0x3F) | 0x80
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fau.set_page(val >> 5)
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return ((val & 0x1F) << 1) | 0x80
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elif op[0] == 'i':
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return int(op[3:]) | 0xC0
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elif op.startswith('0x'):
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@ -241,7 +241,9 @@ def parse_asm(line):
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encoded_src = encode_source(parts[0], fau)
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# Require a word selection for special FAU values
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needs_word_select = ((encoded_src >> 5) == 0b111)
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may_have_word_select = ((encoded_src >> 5) == 0b111)
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# or for regular FAU values
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may_have_word_select |= ((encoded_src >> 6) == 0b10)
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# Has a swizzle been applied yet?
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swizzled = False
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@ -295,13 +297,13 @@ def parse_asm(line):
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val = enums['lanes_8_bit'].bare_values.index(mod)
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encoded |= (val << src.offset['widen'])
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elif mod in ['w0', 'w1']:
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# Chck for special
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die_if(not needs_word_select, 'Unexpected word select')
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# Check whether we may have word select
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die_if(not may_have_word_select, 'Unexpected word select')
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if mod == 'w1':
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encoded_src |= 0x1
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needs_word_select = False
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may_have_word_select = False
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else:
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die(f"Unknown modifier {mod}")
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@ -61,7 +61,9 @@ va_print_src(FILE *fp, unsigned type, unsigned value, unsigned size, unsigned fa
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fprintf(fp, "0x%X", va_immediates[value]);
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}
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} else if (type == VA_SRC_UNIFORM_TYPE) {
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fprintf(fp, "u%u", value | (fau_page << 6));
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fprintf(fp, "u%u", value >> 1 | (fau_page << 5));
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if (size <= 32)
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fprintf(fp, ".w%u", value & 1);
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} else {
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bool discard = (type & 1);
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char *dmark = discard ? "^" : "";
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@ -1,5 +1,5 @@
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02 00 00 00 00 c1 91 00 MOV.i32 r1, r2
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8a 00 00 00 00 c1 91 00 MOV.i32 r1, u10
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8a 00 00 00 00 c1 91 00 MOV.i32 r1, u5.w0
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e3 00 00 00 00 c1 91 02 MOV.i32 r1, thread_local_pointer.w1
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e6 00 00 00 00 c1 91 02 MOV.i32 r1, workgroup_local_pointer.w0
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e2 00 00 00 00 c1 91 06 MOV.i32 r1, lane_id.w0
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@ -25,7 +25,7 @@ e6 00 00 00 00 c1 91 06 MOV.i32 r1, core_id.w0
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01 02 00 0c 70 c0 a0 00 IADD.u32 r0, r1.b3, r2.h1
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01 c9 00 18 00 c0 a0 00 IADD.u32 r0, r1, 0x7060504.b2
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01 02 00 08 20 c0 a1 00 IADD.v2u16 r0, r1, r2
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82 3c 27 20 00 c0 a3 01 SHADDX.u64 [r0:r1], u2, [r60:r61].w0, shift:0x2
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82 3c 27 20 00 c0 a3 01 SHADDX.u64 [r0:r1], u1, [r60:r61].w0, shift:0x2
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40 00 00 18 82 80 60 08 LOAD.i32.unsigned.slot0.wait0 @r0, [r0^:r1^], offset:0
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80 7c 47 20 00 c0 a3 01 SHADDX.u64 [r0:r1], u0, [r60^:r61^].w0, shift:0x4
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40 00 00 38 08 44 61 78 STORE.i128.slot0.end @r4:r5:r6:r7, [r0^:r1^], offset:0
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@ -53,8 +53,8 @@ c0 00 00 00 00 f6 10 01 IADD_IMM.i32 r54, 0x0, #0x0
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f0 00 3c 33 04 40 7f 78 BLEND.slot0.v4.f16.end @r0:r1, blend_descriptor_0.w0, r60, target:0x0
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7b 0d 00 40 04 84 5e 08 LEA_BUF_IMM.slot1.wait0 @r4:r5, r59^, table:0xD, index:0x0
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00 dd c0 08 14 c2 b2 00 FMA.f32 r2, r0, 0x44000000.neg.h1, 0x0.neg
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41 88 c0 00 04 c1 b2 00 FMA.f32 r1, r1^, u8, 0x0.neg
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40 88 c0 00 04 c0 b2 10 FMA.f32.wait1 r0, r0^, u8, 0x0.neg
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41 88 c0 00 04 c1 b2 00 FMA.f32 r1, r1^, u4.w0, 0x0.neg
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40 88 c0 00 04 c0 b2 10 FMA.f32.wait1 r0, r0^, u4.w0, 0x0.neg
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44 00 00 32 06 40 61 78 STORE.i96.estream.slot0.end @r0:r1:r2, [r4^:r5^], offset:0
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44 00 00 39 08 48 61 78 STORE.i128.istream.slot0.end @r8:r9:r10:r11, [r4^:r5^], offset:0
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00 00 00 c0 01 c0 45 48 BARRIER.slot7.wait
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@ -99,7 +99,7 @@ c0 00 00 00 00 c0 10 01 IADD_IMM.i32 r0, 0x0, #0x0
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c0 01 00 00 00 c4 10 51 IADD_IMM.i32.reconverge r4, 0x0, #0x1
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80 00 27 20 00 c2 a3 01 SHADDX.u64 [r2:r3], u0, [r0:r1].w0, shift:0x2
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40 c9 00 10 00 c0 a0 00 IADD.u32 r0, r0^, 0x7060504.b0
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00 82 c0 80 03 c1 f0 00 ICMP_OR.u32.ne.m1 r1, r0, u2, 0x0
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00 82 c0 80 03 c1 f0 00 ICMP_OR.u32.ne.m1 r1, r0, u1.w0, 0x0
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04 00 00 00 00 c5 91 00 MOV.i32 r5, r4
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04 00 00 00 00 c6 91 00 MOV.i32 r6, r4
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04 00 00 00 00 c7 91 08 MOV.i32.wait0 r7, r4
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@ -111,25 +111,25 @@ c0 01 00 00 00 c4 10 51 IADD_IMM.i32.reconverge r4, 0x0, #0x1
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44 00 46 36 28 40 71 78 ST_CVT.slot0.istream.v4.u32.end @r0:r1:r2:r3, [r4^:r5^], r6^, offset:0x0
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7c c0 12 00 26 84 67 00 LEA_TEX_IMM.slot0 @r4:r5:r6, r60^, 0x0, table:0x2, index:0x1
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7c c0 02 00 26 84 67 00 LEA_TEX_IMM.slot0 @r4:r5:r6, r60^, 0x0, table:0x2, index:0x0
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82 81 00 28 f4 82 6a 00 LD_PKA.i64.unsigned.slot0 @r2:r3, u2, u1
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80 81 00 68 f4 80 6a 00 LD_PKA.i64.unsigned.slot1 @r0:r1, u0, u1
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84 81 00 a8 f4 a6 6a 00 LD_PKA.i64.unsigned.slot2 @r38:r39, u4, u1
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83 81 00 a8 f4 a4 6a 00 LD_PKA.i64.unsigned.slot2 @r36:r37, u3, u1
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83 84 00 28 f4 82 6a 00 LD_PKA.i64.unsigned.slot0 @r2:r3, u3, u4
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41 82 00 30 e6 82 6a 00 LD_PKA.i96.unsigned.slot0 @r2:r3:r4, r1^, u2
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40 83 00 30 e6 86 6a 08 LD_PKA.i96.unsigned.slot0.wait0 @r6:r7:r8, r0^, u3
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82 81 00 28 f4 82 6a 00 LD_PKA.i64.unsigned.slot0 @r2:r3, u1.w0, u0.w1
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80 81 00 68 f4 80 6a 00 LD_PKA.i64.unsigned.slot1 @r0:r1, u0.w0, u0.w1
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84 81 00 a8 f4 a6 6a 00 LD_PKA.i64.unsigned.slot2 @r38:r39, u2.w0, u0.w1
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83 81 00 a8 f4 a4 6a 00 LD_PKA.i64.unsigned.slot2 @r36:r37, u1.w1, u0.w1
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83 84 00 28 f4 82 6a 00 LD_PKA.i64.unsigned.slot0 @r2:r3, u1.w1, u2.w0
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41 82 00 30 e6 82 6a 00 LD_PKA.i96.unsigned.slot0 @r2:r3:r4, r1^, u1.w0
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40 83 00 30 e6 86 6a 08 LD_PKA.i96.unsigned.slot0.wait0 @r6:r7:r8, r0^, u1.w1
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40 00 00 00 c0 c0 9c 40 FRCP.f32.wait0126 r0, r0^.neg.abs
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40 44 80 00 00 c0 b8 00 MUX.i32.neg r0, r0^, r4^, u0
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40 44 80 00 01 c0 b8 00 MUX.i32 r0, r0^, r4^, u0
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40 44 80 00 02 c0 b8 00 MUX.i32.fp_zero r0, r0^, r4^, u0
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40 44 80 00 03 c0 b8 00 MUX.i32.bit r0, r0^, r4^, u0
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40 44 80 00 00 c0 b8 00 MUX.i32.neg r0, r0^, r4^, u0.w0
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40 44 80 00 01 c0 b8 00 MUX.i32 r0, r0^, r4^, u0.w0
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40 44 80 00 02 c0 b8 00 MUX.i32.fp_zero r0, r0^, r4^, u0.w0
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40 44 80 00 03 c0 b8 00 MUX.i32.bit r0, r0^, r4^, u0.w0
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00 00 00 01 00 c1 99 68 FREXPM.f32.sqrt.discard r1, r0
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01 00 02 00 00 c2 9c 00 FRSQ.f32 r2, r1
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40 00 02 01 00 c0 99 00 FREXPE.f32.sqrt r0, r0^
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41 42 c0 40 04 c0 62 41 FMA_RSCALE_LEFT.f32.wait0126 r0, r1^, r2^, 0x0.neg, r0^
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42 43 84 85 00 c1 50 01 CSEL.u32.eq r1, r2^, r3^, u4, u5
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42 43 84 85 04 c1 50 01 CSEL.u32.lt r1, r2^, r3^, u4, u5
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42 43 84 85 04 c1 58 01 CSEL.s32.lt r1, r2^, r3^, u4, u5
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42 43 84 85 00 c1 50 01 CSEL.u32.eq r1, r2^, r3^, u2.w0, u2.w1
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42 43 84 85 04 c1 50 01 CSEL.u32.lt r1, r2^, r3^, u2.w0, u2.w1
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42 43 84 85 04 c1 58 01 CSEL.s32.lt r1, r2^, r3^, u2.w0, u2.w1
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3d 00 00 12 b4 82 56 08 LD_VAR_SPECIAL.v2.f32.sample.clobber.slot0.wait0 @r2:r3, r61, index:0x0
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3d 00 00 33 14 82 5d 08 LD_VAR_BUF_IMM.f16.slot0.v4.src_f16.center.retrieve.wait0 @r2:r3, r61, index:0x0
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3d 00 00 33 84 80 5d 08 LD_VAR_BUF_IMM.f16.slot0.v4.src_f16.sample.store.wait0 @r0:r1, r61, index:0x0
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@ -188,9 +188,9 @@ c0 00 00 00 00 c9 10 01 IADD_IMM.i32 r9, 0x0, #0x0
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3d 09 00 00 30 c0 1f 50 BRANCHZ.eq.reconverge r61.h0, offset:9
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0a 00 00 00 00 cb 91 50 MOV.i32.reconverge r11, r10
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00 00 00 00 00 c0 00 48 NOP.wait
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81 0b 80 33 04 8e 78 00 LD_TILE.v4.f16.slot0 @r14:r15, u1, r11, u0
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81 0b 80 33 04 8e 78 00 LD_TILE.v4.f16.slot0 @r14:r15, u0.w1, r11, u0.w0
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0b 00 04 00 00 cc 91 00 CLZ.u32 r12, r11
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82 4c c0 52 00 cc b4 00 RSHIFT_XOR.i32.not_result r12, u2, r12^.b00, 0x0
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82 4c c0 52 00 cc b4 00 RSHIFT_XOR.i32.not_result r12, u1.w0, r12^.b00, 0x0
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4b c0 4c 10 01 cb b4 08 LSHIFT_AND.i32.wait0 r11, r11^, 0x0.b00, r12^
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4f 49 00 28 00 c9 a5 00 FADD.v2f16 r9, r15^, r9^
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4e 48 00 28 00 c8 a5 00 FADD.v2f16 r8, r14^, r8^
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@ -214,15 +214,16 @@ f0 00 3c 32 08 40 7f 78 BLEND.slot0.v4.f32.end @r0:r1:r2:r3, blend_descriptor
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c0 00 00 00 00 f6 10 01 IADD_IMM.i32 r54, 0x0, #0x0
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c0 f1 00 00 10 c1 2f 08 BRANCHZI.eq.absolute.wait0 0x0, blend_descriptor_0.w1
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80 00 c0 17 34 7c 25 01 TEX_FETCH.slot0.f.32.2d @r0:r1:r2:r3, @r60:r61, u0
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80 00 00 00 00 c1 91 02 MOV.i32 r1, u64
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81 00 00 00 00 c1 91 02 MOV.i32 r1, u65
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80 00 00 00 00 c1 91 02 MOV.i32 r1, u32.w0
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81 00 00 00 00 c1 91 02 MOV.i32 r1, u32.w1
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8a 00 00 00 00 c1 91 02 MOV.i32 r1, u37.w0
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30 00 f7 1b 02 cc 20 09 ATOM_RETURN.i32.slot0.axchg.wait0 @r55, @r12, [r48:r49], offset:0x0
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32 00 80 18 02 4c 68 08 ATOM.i32.slot0.aadd.wait0 @r12, [r50:r51], offset:0x0
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32 00 00 18 02 8c 69 08 ATOM1_RETURN.i32.slot0.ainc.wait0 @r12, [r50:r51], offset:0x0
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32 00 00 18 00 80 69 08 ATOM1_RETURN.i32.slot0.ainc.wait0 @, [r50:r51], offset:0x0
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82 00 80 15 b4 80 38 49 VAR_TEX_SINGLE.slot0.skip.sample_store.f.32.2d.zero.wait @r0:r1:r2:r3, u2, u0
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82 20 80 15 b4 80 38 09 VAR_TEX_SINGLE.slot0.skip.sample_store.f.32.2d.computed.wait0 @r0:r1:r2:r3, u2, u0
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82 20 80 1d 84 80 38 41 VAR_TEX_SINGLE.slot0.skip.sample_store.s.32.2d.computed.wait0126 @r0, u2, u0
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82 00 80 15 b4 80 38 49 VAR_TEX_SINGLE.slot0.skip.sample_store.f.32.2d.zero.wait @r0:r1:r2:r3, u1, u0.w0
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82 20 80 15 b4 80 38 09 VAR_TEX_SINGLE.slot0.skip.sample_store.f.32.2d.computed.wait0 @r0:r1:r2:r3, u1, u0.w0
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82 20 80 1d 84 80 38 41 VAR_TEX_SINGLE.slot0.skip.sample_store.s.32.2d.computed.wait0126 @r0, u1, u0.w0
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40 c0 c0 80 03 c0 f0 10 ICMP_OR.u32.ne.m1.wait1 r0, r0^, 0x0, 0x0
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42 43 40 01 01 c0 f8 00 ICMP_AND.s32.gt.i1 r0, r2^, r3^, r0^
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42 c0 c0 c2 03 c0 f0 10 ICMP_MULTI.u32.ne.u1.wait1 r0, r2^, 0x0, 0x0
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@ -561,7 +561,7 @@ GENX(pandecode_fau)(struct pandecode_context *ctx, uint64_t addr,
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fprintf(ctx->dump_stream, "%s @%" PRIx64 ":\n", name, addr);
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for (unsigned i = 0; i < count; ++i) {
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fprintf(ctx->dump_stream, " %08X %08X\n", raw[2 * i], raw[2 * i + 1]);
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fprintf(ctx->dump_stream, "u%d %08X %08X\n", i, raw[2 * i], raw[2 * i + 1]);
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}
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fprintf(ctx->dump_stream, "\n");
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}
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