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ac/surface: overlap color and Z/S fields using a union in gfx9_surf_layout

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Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10083>
This commit is contained in:
Marek Olšák 2021-04-02 16:12:43 -04:00 • committed by Marge Bot
parent ab00557685
commit 988f148db3
2 changed files with 52 additions and 39 deletions
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5
src/amd/common/ac_surface.c
View file

@ -1730,8 +1730,10 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_
/* CMASK fast clear uses these even if FMASK isn't allocated.
* FMASK only supports the Z swizzle modes, whose numbers are multiples of 4.
*/
if (!in->flags.depth) {
surf->u.gfx9.fmask_swizzle_mode = surf->u.gfx9.swizzle_mode & ~0x3;
surf->u.gfx9.fmask_epitch = surf->u.gfx9.epitch;
}
surf->u.gfx9.surf_slice_size = out.sliceSize;
surf->u.gfx9.surf_pitch = out.pitch;
@ -2242,7 +2244,7 @@ static int gfx9_compute_surface(struct ac_addrlib *addrlib, const struct radeon_
if (ac_modifier_has_dcc(surf->modifier)) {
ac_modifier_fill_dcc_params(surf->modifier, surf, &AddrSurfInfoIn);
} else {
} else if (!AddrSurfInfoIn.flags.depth && !AddrSurfInfoIn.flags.stencil) {
/* Optimal values for the L2 cache. */
if (info->chip_class == GFX9) {
surf->u.gfx9.dcc.independent_64B_blocks = 1;
@ -2332,6 +2334,7 @@ static int gfx9_compute_surface(struct ac_addrlib *addrlib, const struct radeon_
surf->htile_size = 0;
surf->htile_slice_size = 0;
surf->u.gfx9.surf_offset = 0;
if (AddrSurfInfoIn.flags.stencil)
surf->u.gfx9.stencil_offset = 0;
surf->cmask_size = 0;
surf->u.gfx9.dcc_retile_use_uint16 = false;

48
src/amd/common/ac_surface.h
View file

@ -165,15 +165,8 @@ struct gfx9_surf_level {
};
struct gfx9_surf_layout {
uint8_t swizzle_mode; /* color or depth */
uint8_t fmask_swizzle_mode;
uint8_t stencil_swizzle_mode;
struct gfx9_surf_meta_flags dcc; /* metadata of color */
uint16_t epitch; /* gfx9 only, not on gfx10 */
uint16_t fmask_epitch; /* gfx9 only, not on gfx10 */
uint16_t stencil_epitch; /* gfx9 only, not on gfx10 */
uint8_t swizzle_mode; /* color or depth */
enum gfx9_resource_type resource_type:8; /* 1D, 2D or 3D */
uint16_t surf_pitch; /* in blocks */
@ -190,7 +183,20 @@ struct gfx9_surf_layout {
uint16_t base_mip_width;
uint16_t base_mip_height;
uint64_t stencil_offset; /* separate stencil */
/* Pitch of level in blocks, only valid for prt images. */
uint16_t prt_level_pitch[RADEON_SURF_MAX_LEVELS];
/* Offset within slice in bytes, only valid for prt images. */
uint32_t prt_level_offset[RADEON_SURF_MAX_LEVELS];
union {
/* Color */
struct {
struct gfx9_surf_meta_flags dcc; /* metadata of color */
uint8_t fmask_swizzle_mode;
uint16_t fmask_epitch; /* gfx9 only, not on gfx10 */
uint16_t dcc_pitch_max;
uint16_t dcc_height;
uint8_t dcc_block_width;
uint8_t dcc_block_height;
@ -201,27 +207,31 @@ struct gfx9_surf_layout {
* All other chips must set rb_aligned=1.
* A compute shader needs to convert from aligned DCC to unaligned.
*/
uint32_t display_dcc_size;
uint8_t display_dcc_alignment_log2;
uint32_t display_dcc_size;
uint16_t display_dcc_pitch_max; /* (mip chain pitch - 1) */
uint16_t dcc_pitch_max;
uint16_t display_dcc_height;
bool dcc_retile_use_uint16; /* if all values fit into uint16_t */
uint32_t dcc_retile_num_elements;
void *dcc_retile_map;
/* Offset within slice in bytes, only valid for prt images. */
uint32_t prt_level_offset[RADEON_SURF_MAX_LEVELS];
/* Pitch of level in blocks, only valid for prt images. */
uint16_t prt_level_pitch[RADEON_SURF_MAX_LEVELS];
/* DCC level info */
struct gfx9_surf_level dcc_levels[RADEON_SURF_MAX_LEVELS];
/* HTILE level info */
struct gfx9_surf_level htile_levels[RADEON_SURF_MAX_LEVELS];
/* CMASK level info (only level 0) */
struct gfx9_surf_level cmask_level0;
};
/* Z/S */
struct {
uint64_t stencil_offset; /* separate stencil */
uint16_t stencil_epitch; /* gfx9 only, not on gfx10 */
uint8_t stencil_swizzle_mode;
/* HTILE level info */
struct gfx9_surf_level htile_levels[RADEON_SURF_MAX_LEVELS];
};
};
};
struct radeon_surf {