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ac/surface: pack alignments by storing log2 in radeon_surf

Browse source 
Only one bit is set in alignments, so store the bit offset (log2) and
change the type from uint32_t to uint8_t.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10083>
This commit is contained in:
Marek Olšák 2021-04-02 14:59:54 -04:00 • committed by Marge Bot
parent cb016bb600
commit ab00557685
11 changed files with 80 additions and 78 deletions
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86
src/amd/common/ac_surface.c
View file

@ -857,7 +857,7 @@ static int gfx6_compute_level(ADDR_HANDLE addrlib, const struct ac_surf_config *
dcc_level->dcc_offset = surf->dcc_size;
surf->num_dcc_levels = level + 1;
surf->dcc_size = dcc_level->dcc_offset + AddrDccOut->dccRamSize;
surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);
surf->dcc_alignment_log2 = MAX2(surf->dcc_alignment_log2, util_logbase2(AddrDccOut->dccRamBaseAlign));
/* If the DCC size of a subresource (1 mip level or 1 slice)
* is not aligned, the DCC memory layout is not contiguous for
@ -935,7 +935,7 @@ static int gfx6_compute_level(ADDR_HANDLE addrlib, const struct ac_surf_config *
if (ret == ADDR_OK) {
surf->htile_size = AddrHtileOut->htileBytes;
surf->htile_slice_size = AddrHtileOut->sliceSize;
surf->htile_alignment = AddrHtileOut->baseAlign;
surf->htile_alignment_log2 = util_logbase2(AddrHtileOut->baseAlign);
surf->num_htile_levels = level + 1;
}
}
@ -1007,7 +1007,7 @@ static int gfx6_surface_settings(ADDR_HANDLE addrlib, const struct radeon_info *
const struct ac_surf_config *config,
ADDR_COMPUTE_SURFACE_INFO_OUTPUT *csio, struct radeon_surf *surf)
{
surf->surf_alignment = csio->baseAlign;
surf->surf_alignment_log2 = util_logbase2(csio->baseAlign);
surf->u.legacy.pipe_config = csio->pTileInfo->pipeConfig - 1;
gfx6_set_micro_tile_mode(surf, info);
@ -1108,7 +1108,7 @@ static void ac_compute_cmask(const struct radeon_info *info, const struct ac_sur
else
num_layers = config->info.array_size;
surf->cmask_alignment = MAX2(256, base_align);
surf->cmask_alignment_log2 = util_logbase2(MAX2(256, base_align));
surf->cmask_slice_size = align(slice_bytes, base_align);
surf->cmask_size = surf->cmask_slice_size * num_layers;
}
@ -1326,10 +1326,10 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *i
surf->num_dcc_levels = 0;
surf->surf_size = 0;
surf->dcc_size = 0;
surf->dcc_alignment = 1;
surf->dcc_alignment_log2 = 0;
surf->htile_size = 0;
surf->htile_slice_size = 0;
surf->htile_alignment = 1;
surf->htile_alignment_log2 = 0;
const bool only_stencil =
(surf->flags & RADEON_SURF_SBUFFER) && !(surf->flags & RADEON_SURF_ZBUFFER);
@ -1428,7 +1428,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *i
return r;
surf->fmask_size = fout.fmaskBytes;
surf->fmask_alignment = fout.baseAlign;
surf->fmask_alignment_log2 = util_logbase2(fout.baseAlign);
surf->fmask_slice_size = fout.sliceSize;
surf->fmask_tile_swizzle = 0;
@ -1477,7 +1477,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *i
*
* "dcc_alignment * 4" was determined by trial and error.
*/
surf->dcc_size = align64(surf->surf_size >> 8, surf->dcc_alignment * 4);
surf->dcc_size = align64(surf->surf_size >> 8, (1 << surf->dcc_alignment_log2) * 4);
}
/* Make sure HTILE covers the whole miptree, because the shader reads
@ -1491,7 +1491,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *i
const unsigned htile_element_size = 4;
surf->htile_size = (total_pixels / htile_block_size) * htile_element_size;
surf->htile_size = align(surf->htile_size, surf->htile_alignment);
surf->htile_size = align(surf->htile_size, 1 << surf->htile_alignment_log2);
} else if (!surf->htile_size) {
/* Unset this if HTILE is not present. */
surf->flags &= ~RADEON_SURF_TC_COMPATIBLE_HTILE;
@ -1718,7 +1718,7 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_
surf->u.gfx9.stencil_swizzle_mode = in->swizzleMode;
surf->u.gfx9.stencil_epitch =
out.epitchIsHeight ? out.mipChainHeight - 1 : out.mipChainPitch - 1;
surf->surf_alignment = MAX2(surf->surf_alignment, out.baseAlign);
surf->surf_alignment_log2 = MAX2(surf->surf_alignment_log2, util_logbase2(out.baseAlign));
surf->u.gfx9.stencil_offset = align(surf->surf_size, out.baseAlign);
surf->surf_size = surf->u.gfx9.stencil_offset + out.surfSize;
return 0;
@ -1737,7 +1737,7 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_
surf->u.gfx9.surf_pitch = out.pitch;
surf->u.gfx9.surf_height = out.height;
surf->surf_size = out.surfSize;
surf->surf_alignment = out.baseAlign;
surf->surf_alignment_log2 = util_logbase2(out.baseAlign);
if (!compressed && surf->blk_w > 1 && out.pitch == out.pixelPitch &&
surf->u.gfx9.swizzle_mode == ADDR_SW_LINEAR) {
@ -1800,7 +1800,7 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_
surf->htile_size = hout.htileBytes;
surf->htile_slice_size = hout.sliceSize;
surf->htile_alignment = hout.baseAlign;
surf->htile_alignment_log2 = util_logbase2(hout.baseAlign);
surf->num_htile_levels = in->numMipLevels;
for (unsigned i = 0; i < in->numMipLevels; i++) {
@ -1888,9 +1888,10 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_
surf->u.gfx9.dcc_block_width = dout.compressBlkWidth;
surf->u.gfx9.dcc_block_height = dout.compressBlkHeight;
surf->u.gfx9.dcc_block_depth = dout.compressBlkDepth;
surf->u.gfx9.dcc_pitch_max = dout.pitch - 1;
surf->dcc_size = dout.dccRamSize;
surf->dcc_slice_size = dout.dccRamSliceSize;
surf->dcc_alignment = dout.dccRamBaseAlign;
surf->dcc_alignment_log2 = util_logbase2(dout.dccRamBaseAlign);
surf->num_dcc_levels = in->numMipLevels;
/* Disable DCC for levels that are in the mip tail.
@ -1938,9 +1939,8 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_
surf->dcc_size = 0;
surf->u.gfx9.display_dcc_size = surf->dcc_size;
surf->u.gfx9.display_dcc_alignment = surf->dcc_alignment;
surf->u.gfx9.display_dcc_pitch_max = dout.pitch - 1;
surf->u.gfx9.dcc_pitch_max = dout.pitch - 1;
surf->u.gfx9.display_dcc_alignment_log2 = surf->dcc_alignment_log2;
surf->u.gfx9.display_dcc_pitch_max = surf->u.gfx9.dcc_pitch_max;
/* Compute displayable DCC. */
if (((in->flags.display && info->use_display_dcc_with_retile_blit) ||
@ -1960,7 +1960,7 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_
return ret;
surf->u.gfx9.display_dcc_size = dout.dccRamSize;
surf->u.gfx9.display_dcc_alignment = dout.dccRamBaseAlign;
surf->u.gfx9.display_dcc_alignment_log2 = util_logbase2(dout.dccRamBaseAlign);
surf->u.gfx9.display_dcc_pitch_max = dout.pitch - 1;
assert(surf->u.gfx9.display_dcc_size <= surf->dcc_size);
@ -2068,7 +2068,7 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_
surf->u.gfx9.fmask_swizzle_mode = fin.swizzleMode;
surf->u.gfx9.fmask_epitch = fout.pitch - 1;
surf->fmask_size = fout.fmaskBytes;
surf->fmask_alignment = fout.baseAlign;
surf->fmask_alignment_log2 = util_logbase2(fout.baseAlign);
surf->fmask_slice_size = fout.sliceSize;
/* Compute tile swizzle for the FMASK surface. */
@ -2133,7 +2133,7 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_
return ret;
surf->cmask_size = cout.cmaskBytes;
surf->cmask_alignment = cout.baseAlign;
surf->cmask_alignment_log2 = util_logbase2(cout.baseAlign);
surf->cmask_slice_size = cout.sliceSize;
surf->u.gfx9.cmask_level0.offset = meta_mip_info[0].offset;
surf->u.gfx9.cmask_level0.size = meta_mip_info[0].sliceSize;
@ -2404,7 +2404,7 @@ static int gfx9_compute_surface(struct ac_addrlib *addrlib, const struct radeon_
if (info->has_graphics && !compressed && !config->is_3d && config->info.levels == 1 &&
AddrSurfInfoIn.flags.color && !surf->is_linear &&
surf->surf_alignment >= 64 * 1024 && /* 64KB tiling */
(1 << surf->surf_alignment_log2) >= 64 * 1024 && /* 64KB tiling */
!(surf->flags & (RADEON_SURF_DISABLE_DCC | RADEON_SURF_FORCE_SWIZZLE_MODE |
RADEON_SURF_FORCE_MICRO_TILE_MODE)) &&
(surf->modifier == DRM_FORMAT_MOD_INVALID ||
@ -2500,7 +2500,7 @@ int ac_compute_surface(struct ac_addrlib *addrlib, const struct radeon_info *inf
/* Determine the memory layout of multiple allocations in one buffer. */
surf->total_size = surf->surf_size;
surf->alignment = surf->surf_alignment;
surf->alignment_log2 = surf->surf_alignment_log2;
/* Ensure the offsets are always 0 if not available. */
surf->dcc_offset = surf->display_dcc_offset = 0;
@ -2508,23 +2508,23 @@ int ac_compute_surface(struct ac_addrlib *addrlib, const struct radeon_info *inf
surf->htile_offset = 0;
if (surf->htile_size) {
surf->htile_offset = align64(surf->total_size, surf->htile_alignment);
surf->htile_offset = align64(surf->total_size, 1 << surf->htile_alignment_log2);
surf->total_size = surf->htile_offset + surf->htile_size;
surf->alignment = MAX2(surf->alignment, surf->htile_alignment);
surf->alignment_log2 = MAX2(surf->alignment_log2, surf->htile_alignment_log2);
}
if (surf->fmask_size) {
assert(config->info.samples >= 2);
surf->fmask_offset = align64(surf->total_size, surf->fmask_alignment);
surf->fmask_offset = align64(surf->total_size, 1 << surf->fmask_alignment_log2);
surf->total_size = surf->fmask_offset + surf->fmask_size;
surf->alignment = MAX2(surf->alignment, surf->fmask_alignment);
surf->alignment_log2 = MAX2(surf->alignment_log2, surf->fmask_alignment_log2);
}
/* Single-sample CMASK is in a separate buffer. */
if (surf->cmask_size && config->info.samples >= 2) {
surf->cmask_offset = align64(surf->total_size, surf->cmask_alignment);
surf->cmask_offset = align64(surf->total_size, 1 << surf->cmask_alignment_log2);
surf->total_size = surf->cmask_offset + surf->cmask_size;
surf->alignment = MAX2(surf->alignment, surf->cmask_alignment);
surf->alignment_log2 = MAX2(surf->alignment_log2, surf->cmask_alignment_log2);
}
if (surf->is_displayable)
@ -2538,13 +2538,13 @@ int ac_compute_surface(struct ac_addrlib *addrlib, const struct radeon_info *inf
*/
if (info->chip_class >= GFX9 && surf->u.gfx9.dcc_retile_num_elements) {
/* Add space for the displayable DCC buffer. */
surf->display_dcc_offset = align64(surf->total_size, surf->u.gfx9.display_dcc_alignment);
surf->display_dcc_offset = align64(surf->total_size, 1 << surf->u.gfx9.display_dcc_alignment_log2);
surf->total_size = surf->display_dcc_offset + surf->u.gfx9.display_dcc_size;
}
surf->dcc_offset = align64(surf->total_size, surf->dcc_alignment);
surf->dcc_offset = align64(surf->total_size, 1 << surf->dcc_alignment_log2);
surf->total_size = surf->dcc_offset + surf->dcc_size;
surf->alignment = MAX2(surf->alignment, surf->dcc_alignment);
surf->alignment_log2 = MAX2(surf->alignment_log2, surf->dcc_alignment_log2);
}
return 0;
@ -2557,7 +2557,7 @@ void ac_surface_zero_dcc_fields(struct radeon_surf *surf)
surf->display_dcc_offset = 0;
if (!surf->htile_offset && !surf->fmask_offset && !surf->cmask_offset) {
surf->total_size = surf->surf_size;
surf->alignment = surf->surf_alignment;
surf->alignment_log2 = surf->surf_alignment_log2;
}
}
@ -2931,7 +2931,7 @@ bool ac_surface_override_offset_stride(const struct radeon_info *info, struct ra
}
}
if (offset & (surf->alignment - 1) ||
if (offset & ((1 << surf->alignment_log2) - 1) ||
offset >= UINT64_MAX - surf->total_size)
return false;
@ -3037,7 +3037,7 @@ void ac_surface_print_info(FILE *out, const struct radeon_info *info,
"alignment=%u, swmode=%u, epitch=%u, pitch=%u, blk_w=%u, "
"blk_h=%u, bpe=%u, flags=0x%"PRIx64"\n",
surf->surf_size, surf->u.gfx9.surf_slice_size,
surf->surf_alignment, surf->u.gfx9.swizzle_mode,
1 << surf->surf_alignment_log2, surf->u.gfx9.swizzle_mode,
surf->u.gfx9.epitch, surf->u.gfx9.surf_pitch,
surf->blk_w, surf->blk_h, surf->bpe, surf->flags);
@ -3046,7 +3046,7 @@ void ac_surface_print_info(FILE *out, const struct radeon_info *info,
" FMask: offset=%" PRIu64 ", size=%" PRIu64 ", "
"alignment=%u, swmode=%u, epitch=%u\n",
surf->fmask_offset, surf->fmask_size,
surf->fmask_alignment, surf->u.gfx9.fmask_swizzle_mode,
1 << surf->fmask_alignment_log2, surf->u.gfx9.fmask_swizzle_mode,
surf->u.gfx9.fmask_epitch);
if (surf->cmask_offset)
@ -3054,19 +3054,19 @@ void ac_surface_print_info(FILE *out, const struct radeon_info *info,
" CMask: offset=%" PRIu64 ", size=%u, "
"alignment=%u\n",
surf->cmask_offset, surf->cmask_size,
surf->cmask_alignment);
1 << surf->cmask_alignment_log2);
if (surf->htile_offset)
fprintf(out,
" HTile: offset=%" PRIu64 ", size=%u, alignment=%u\n",
surf->htile_offset, surf->htile_size,
surf->htile_alignment);
1 << surf->htile_alignment_log2);
if (surf->dcc_offset)
fprintf(out,
" DCC: offset=%" PRIu64 ", size=%u, "
"alignment=%u, pitch_max=%u, num_dcc_levels=%u\n",
surf->dcc_offset, surf->dcc_size, surf->dcc_alignment,
surf->dcc_offset, surf->dcc_size, 1 << surf->dcc_alignment_log2,
surf->u.gfx9.display_dcc_pitch_max, surf->num_dcc_levels);
if (surf->u.gfx9.stencil_offset)
@ -3079,13 +3079,13 @@ void ac_surface_print_info(FILE *out, const struct radeon_info *info,
fprintf(out,
" Surf: size=%" PRIu64 ", alignment=%u, blk_w=%u, blk_h=%u, "
"bpe=%u, flags=0x%"PRIx64"\n",
surf->surf_size, surf->surf_alignment, surf->blk_w,
surf->surf_size, 1 << surf->surf_alignment_log2, surf->blk_w,
surf->blk_h, surf->bpe, surf->flags);
fprintf(out,
" Layout: size=%" PRIu64 ", alignment=%u, bankw=%u, bankh=%u, "
"nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
surf->surf_size, surf->surf_alignment,
surf->surf_size, 1 << surf->surf_alignment_log2,
surf->u.legacy.bankw, surf->u.legacy.bankh,
surf->u.legacy.num_banks, surf->u.legacy.mtilea,
surf->u.legacy.tile_split, surf->u.legacy.pipe_config,
@ -3097,7 +3097,7 @@ void ac_surface_print_info(FILE *out, const struct radeon_info *info,
"alignment=%u, pitch_in_pixels=%u, bankh=%u, "
"slice_tile_max=%u, tile_mode_index=%u\n",
surf->fmask_offset, surf->fmask_size,
surf->fmask_alignment, surf->u.legacy.fmask.pitch_in_pixels,
1 << surf->fmask_alignment_log2, surf->u.legacy.fmask.pitch_in_pixels,
surf->u.legacy.fmask.bankh,
surf->u.legacy.fmask.slice_tile_max,
surf->u.legacy.fmask.tiling_index);
@ -3107,16 +3107,16 @@ void ac_surface_print_info(FILE *out, const struct radeon_info *info,
" CMask: offset=%" PRIu64 ", size=%u, alignment=%u, "
"slice_tile_max=%u\n",
surf->cmask_offset, surf->cmask_size,
surf->cmask_alignment, surf->u.legacy.cmask_slice_tile_max);
1 << surf->cmask_alignment_log2, surf->u.legacy.cmask_slice_tile_max);
if (surf->htile_offset)
fprintf(out, " HTile: offset=%" PRIu64 ", size=%u, alignment=%u\n",
surf->htile_offset, surf->htile_size,
surf->htile_alignment);
1 << surf->htile_alignment_log2);
if (surf->dcc_offset)
fprintf(out, " DCC: offset=%" PRIu64 ", size=%u, alignment=%u\n",
surf->dcc_offset, surf->dcc_size, surf->dcc_alignment);
surf->dcc_offset, surf->dcc_size, 1 << surf->dcc_alignment_log2);
if (surf->has_stencil)
fprintf(out, " StencilLayout: tilesplit=%u\n",

16
src/amd/common/ac_surface.h
View file

@ -202,7 +202,7 @@ struct gfx9_surf_layout {
* A compute shader needs to convert from aligned DCC to unaligned.
*/
uint32_t display_dcc_size;
uint32_t display_dcc_alignment;
uint8_t display_dcc_alignment_log2;
uint16_t display_dcc_pitch_max; /* (mip chain pitch - 1) */
uint16_t dcc_pitch_max;
bool dcc_retile_use_uint16; /* if all values fit into uint16_t */
@ -276,24 +276,27 @@ struct radeon_surf {
uint8_t tile_swizzle;
uint8_t fmask_tile_swizzle;
/* Use (1 << log2) to compute the alignment. */
uint8_t surf_alignment_log2;
uint8_t fmask_alignment_log2;
uint8_t dcc_alignment_log2;
uint8_t htile_alignment_log2;
uint8_t cmask_alignment_log2;
uint8_t alignment_log2;
uint64_t surf_size;
uint64_t fmask_size;
uint32_t surf_alignment;
uint32_t fmask_alignment;
uint64_t fmask_slice_size;
/* DCC and HTILE are very small. */
uint32_t dcc_size;
uint32_t dcc_slice_size;
uint32_t dcc_alignment;
uint32_t htile_size;
uint32_t htile_slice_size;
uint32_t htile_alignment;
uint32_t cmask_size;
uint32_t cmask_slice_size;
uint32_t cmask_alignment;
/* All buffers combined. */
uint64_t htile_offset;
@ -302,7 +305,6 @@ struct radeon_surf {
uint64_t dcc_offset;
uint64_t display_dcc_offset;
uint64_t total_size;
uint32_t alignment;
union {
/* Return values for GFX8 and older.

2
src/amd/vulkan/radv_device.c
View file

@ -6364,7 +6364,7 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff
va += plane->surface.u.legacy.dcc_level[iview->base_mip].dcc_offset;
unsigned dcc_tile_swizzle = surf->tile_swizzle;
dcc_tile_swizzle &= (surf->dcc_alignment - 1) >> 8;
dcc_tile_swizzle &= ((1 << surf->dcc_alignment_log2) - 1) >> 8;
cb->cb_dcc_base = va >> 8;
cb->cb_dcc_base |= dcc_tile_swizzle;

10
src/amd/vulkan/radv_image.c
View file

@ -705,7 +705,7 @@ si_set_mutable_tex_desc_fields(struct radv_device *device, struct radv_image *im
meta_va += plane->surface.u.legacy.dcc_level[base_level].dcc_offset;
unsigned dcc_tile_swizzle = plane->surface.tile_swizzle << 8;
dcc_tile_swizzle &= plane->surface.dcc_alignment - 1;
dcc_tile_swizzle &= (1 << plane->surface.dcc_alignment_log2) - 1;
meta_va |= dcc_tile_swizzle;
} else if (!disable_compression && radv_image_is_tc_compat_htile(image)) {
meta_va = gpu_address + plane->surface.htile_offset;
@ -1261,9 +1261,9 @@ radv_image_alloc_single_sample_cmask(const struct radv_device *device,
assert(image->info.storage_samples == 1);
surf->cmask_offset = align64(surf->total_size, surf->cmask_alignment);
surf->cmask_offset = align64(surf->total_size, 1 << surf->cmask_alignment_log2);
surf->total_size = surf->cmask_offset + surf->cmask_size;
surf->alignment = MAX2(surf->alignment, surf->cmask_alignment);
surf->alignment_log2 = MAX2(surf->alignment_log2, surf->cmask_alignment_log2);
}
static void
@ -1410,7 +1410,7 @@ radv_image_create_layout(struct radv_device *device, struct radv_image_create_in
offset = mod_info->pPlaneLayouts[plane].offset;
stride = mod_info->pPlaneLayouts[plane].rowPitch / image->planes[plane].surface.bpe;
} else {
offset = align(image->size, image->planes[plane].surface.alignment);
offset = align(image->size, 1 << image->planes[plane].surface.alignment_log2);
stride = 0; /* 0 means no override */
}
@ -1434,7 +1434,7 @@ radv_image_create_layout(struct radv_device *device, struct radv_image_create_in
}
image->size = MAX2(image->size, offset + image->planes[plane].surface.total_size);
image->alignment = MAX2(image->alignment, image->planes[plane].surface.alignment);
image->alignment = MAX2(image->alignment, 1 << image->planes[plane].surface.alignment_log2);
image->planes[plane].format = vk_format_get_plane_format(image->vk_format, plane);
}

12
src/gallium/drivers/r600/r600_texture.c
View file

@ -653,7 +653,7 @@ void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
out->pitch_in_pixels = fmask.u.legacy.level[0].nblk_x;
out->bank_height = fmask.u.legacy.bankh;
out->tile_swizzle = fmask.tile_swizzle;
out->alignment = MAX2(256, fmask.surf_alignment);
out->alignment = MAX2(256, 1 << fmask.surf_alignment_log2);
out->size = fmask.surf_size;
}
@ -804,7 +804,7 @@ static void r600_texture_get_htile_size(struct r600_common_screen *rscreen,
pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
base_align = num_pipes * pipe_interleave_bytes;
rtex->surface.htile_alignment = base_align;
rtex->surface.htile_alignment_log2 = util_logbase2(base_align);
rtex->surface.htile_size =
util_num_layers(&rtex->resource.b.b, 0) *
align(slice_bytes, base_align);
@ -818,7 +818,7 @@ static void r600_texture_allocate_htile(struct r600_common_screen *rscreen,
if (!rtex->surface.htile_size)
return;
rtex->htile_offset = align(rtex->size, rtex->surface.htile_alignment);
rtex->htile_offset = align(rtex->size, 1 << rtex->surface.htile_alignment_log2);
rtex->size = rtex->htile_offset + rtex->surface.htile_size;
}
@ -840,7 +840,7 @@ void r600_print_texture_info(struct r600_common_screen *rscreen,
u_log_printf(log, " Layout: size=%"PRIu64", alignment=%u, bankw=%u, "
"bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
rtex->surface.surf_size, rtex->surface.surf_alignment, rtex->surface.u.legacy.bankw,
rtex->surface.surf_size, 1 << rtex->surface.surf_alignment_log2, rtex->surface.u.legacy.bankw,
rtex->surface.u.legacy.bankh, rtex->surface.u.legacy.num_banks, rtex->surface.u.legacy.mtilea,
rtex->surface.u.legacy.tile_split, rtex->surface.u.legacy.pipe_config,
(rtex->surface.flags & RADEON_SURF_SCANOUT) != 0);
@ -862,7 +862,7 @@ void r600_print_texture_info(struct r600_common_screen *rscreen,
u_log_printf(log, " HTile: offset=%"PRIu64", size=%u "
"alignment=%u\n",
rtex->htile_offset, rtex->surface.htile_size,
rtex->surface.htile_alignment);
1 << rtex->surface.htile_alignment_log2);
for (i = 0; i <= rtex->resource.b.b.last_level; i++)
u_log_printf(log, " Level[%i]: offset=%"PRIu64", slice_size=%"PRIu64", "
@ -971,7 +971,7 @@ r600_texture_create_object(struct pipe_screen *screen,
/* Now create the backing buffer. */
if (!buf) {
r600_init_resource_fields(rscreen, resource, rtex->size,
rtex->surface.surf_alignment);
1 << rtex->surface.surf_alignment_log2);
if (!r600_alloc_resource(rscreen, resource)) {
FREE(rtex);

2
src/gallium/drivers/r600/radeon_video.c
View file

@ -171,7 +171,7 @@ void rvid_join_surfaces(struct r600_common_context *rctx,
continue;
/* adjust the texture layer offsets */
off = align(off, surfaces[i]->surf_alignment);
off = align(off, 1 << surfaces[i]->surf_alignment_log2);
/* copy the tiling parameters */
surfaces[i]->u.legacy.bankw = surfaces[best_tiling]->u.legacy.bankw;

2
src/gallium/drivers/radeonsi/si_clear.c
View file

@ -90,7 +90,7 @@ static bool si_alloc_separate_cmask(struct si_screen *sscreen, struct si_texture
tex->cmask_buffer =
si_aligned_buffer_create(&sscreen->b, SI_RESOURCE_FLAG_UNMAPPABLE, PIPE_USAGE_DEFAULT,
tex->surface.cmask_size, tex->surface.cmask_alignment);
tex->surface.cmask_size, 1 << tex->surface.cmask_alignment_log2);
if (tex->cmask_buffer == NULL)
return false;

2
src/gallium/drivers/radeonsi/si_descriptors.c
View file

@ -340,7 +340,7 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture
}
unsigned dcc_tile_swizzle = tex->surface.tile_swizzle << 8;
dcc_tile_swizzle &= tex->surface.dcc_alignment - 1;
dcc_tile_swizzle &= (1 << tex->surface.dcc_alignment_log2) - 1;
meta_va |= dcc_tile_swizzle;
} else if (vi_tc_compat_htile_enabled(tex, first_level,
is_stencil ? PIPE_MASK_S : PIPE_MASK_Z)) {

2
src/gallium/drivers/radeonsi/si_state.c
View file

@ -3035,7 +3035,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
8;
unsigned dcc_tile_swizzle = tex->surface.tile_swizzle;
dcc_tile_swizzle &= (tex->surface.dcc_alignment - 1) >> 8;
dcc_tile_swizzle &= ((1 << tex->surface.dcc_alignment_log2) - 1) >> 8;
cb_dcc_base |= dcc_tile_swizzle;
}

8
src/gallium/drivers/radeonsi/si_texture.c
View file

@ -1310,9 +1310,9 @@ si_texture_create_with_modifier(struct pipe_screen *screen,
is_flushed_depth, tc_compatible_htile))
return NULL;
plane_offset[i] = align64(total_size, surface[i].surf_alignment);
plane_offset[i] = align64(total_size, 1 << surface[i].surf_alignment_log2);
total_size = plane_offset[i] + surface[i].total_size;
max_alignment = MAX2(max_alignment, surface[i].surf_alignment);
max_alignment = MAX2(max_alignment, 1 << surface[i].surf_alignment_log2);
}
struct si_texture *plane0 = NULL, *last_plane = NULL;
@ -1625,7 +1625,7 @@ static struct pipe_resource *si_texture_from_winsys_buffer(struct si_screen *ssc
if (ac_surface_get_plane_offset(sscreen->info.chip_class, &tex->surface, 0, 0) +
tex->surface.total_size > buf->size ||
1 << buf->alignment_log2 < tex->surface.alignment) {
buf->alignment_log2 < tex->surface.alignment_log2) {
si_texture_reference(&tex, NULL);
return NULL;
}
@ -2366,7 +2366,7 @@ void vi_separate_dcc_try_enable(struct si_context *sctx, struct si_texture *tex)
} else {
tex->dcc_separate_buffer =
si_aligned_buffer_create(sctx->b.screen, SI_RESOURCE_FLAG_UNMAPPABLE, PIPE_USAGE_DEFAULT,
tex->surface.dcc_size, tex->surface.dcc_alignment);
tex->surface.dcc_size, 1 << tex->surface.dcc_alignment_log2);
if (!tex->dcc_separate_buffer)
return;
}

16
src/gallium/winsys/radeon/drm/radeon_drm_surface.c
View file

@ -146,7 +146,7 @@ static void surf_winsys_to_drm(struct radeon_surface *surf_drm,
}
surf_drm->bo_size = surf_ws->surf_size;
surf_drm->bo_alignment = surf_ws->surf_alignment;
surf_drm->bo_alignment = 1 << surf_ws->surf_alignment_log2;
surf_drm->bankw = surf_ws->u.legacy.bankw;
surf_drm->bankh = surf_ws->u.legacy.bankh;
@ -188,7 +188,7 @@ static void surf_drm_to_winsys(struct radeon_drm_winsys *ws,
surf_ws->flags = surf_drm->flags;
surf_ws->surf_size = surf_drm->bo_size;
surf_ws->surf_alignment = surf_drm->bo_alignment;
surf_ws->surf_alignment_log2 = util_logbase2(surf_drm->bo_alignment);
surf_ws->u.legacy.bankw = surf_drm->bankw;
surf_ws->u.legacy.bankh = surf_drm->bankh;
@ -276,7 +276,7 @@ static void si_compute_cmask(const struct radeon_info *info,
else
num_layers = config->info.array_size;
surf->cmask_alignment = MAX2(256, base_align);
surf->cmask_alignment_log2 = util_logbase2(MAX2(256, base_align));
surf->cmask_size = align(slice_bytes, base_align) * num_layers;
}
@ -342,7 +342,7 @@ static void si_compute_htile(const struct radeon_info *info,
pipe_interleave_bytes = info->pipe_interleave_bytes;
base_align = num_pipes * pipe_interleave_bytes;
surf->htile_alignment = base_align;
surf->htile_alignment_log2 = util_logbase2(base_align);
surf->htile_size = num_layers * align(slice_bytes, base_align);
}
@ -404,7 +404,7 @@ static int radeon_winsys_surface_init(struct radeon_winsys *rws,
assert(fmask.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
surf_ws->fmask_size = fmask.surf_size;
surf_ws->fmask_alignment = MAX2(256, fmask.surf_alignment);
surf_ws->fmask_alignment_log2 = util_logbase2(MAX2(256, 1 << fmask.surf_alignment_log2));
surf_ws->fmask_tile_swizzle = fmask.tile_swizzle;
surf_ws->u.legacy.fmask.slice_tile_max =
@ -439,19 +439,19 @@ static int radeon_winsys_surface_init(struct radeon_winsys *rws,
surf_ws->total_size = surf_ws->surf_size;
if (surf_ws->htile_size) {
surf_ws->htile_offset = align64(surf_ws->total_size, surf_ws->htile_alignment);
surf_ws->htile_offset = align64(surf_ws->total_size, 1 << surf_ws->htile_alignment_log2);
surf_ws->total_size = surf_ws->htile_offset + surf_ws->htile_size;
}
if (surf_ws->fmask_size) {
assert(tex->nr_samples >= 2);
surf_ws->fmask_offset = align64(surf_ws->total_size, surf_ws->fmask_alignment);
surf_ws->fmask_offset = align64(surf_ws->total_size, 1 << surf_ws->fmask_alignment_log2);
surf_ws->total_size = surf_ws->fmask_offset + surf_ws->fmask_size;
}
/* Single-sample CMASK is in a separate buffer. */
if (surf_ws->cmask_size && tex->nr_samples >= 2) {
surf_ws->cmask_offset = align64(surf_ws->total_size, surf_ws->cmask_alignment);
surf_ws->cmask_offset = align64(surf_ws->total_size, 1 << surf_ws->cmask_alignment_log2);
surf_ws->total_size = surf_ws->cmask_offset + surf_ws->cmask_size;
}
}