From 971709661d5ca5c4b94c67379827f86335becf8b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Tapani=20P=C3=A4lli?= <tapani.palli@intel.com>
Date: Thu, 5 Feb 2026 10:09:34 +0200
Subject: [PATCH] intel/genxml: add CHICKEN_RASTER_2 with required bit for Xe3
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Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
(cherry picked from commit 61b5e91bbaf288463265070b30f5183b7c1ee7c7)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39969>
---
 .pick_status.json           | 2 +-
 src/intel/genxml/gen300.xml | 4 ++++
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/.pick_status.json b/.pick_status.json
index 198747bbff4..f477c25028a 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -1124,7 +1124,7 @@
         "description": "intel/genxml: add CHICKEN_RASTER_2 with required bit for Xe3",
         "nominated": true,
         "nomination_type": 1,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": null,
         "notes": null
diff --git a/src/intel/genxml/gen300.xml b/src/intel/genxml/gen300.xml
index 090747aaf29..77ee56e36ce 100644
--- a/src/intel/genxml/gen300.xml
+++ b/src/intel/genxml/gen300.xml
@@ -809,4 +809,8 @@
     <field name="UAV Coherency Mode Mask" dword="2" bits="22:22" type="uint" />
     <field name="Memory allocation for Scratch and Midthread Preemption buffers Mask" dword="2" bits="27:27" type="uint" />
   </instruction>
+  <register name="CHICKEN_RASTER_2" length="1" num="0x6208">
+    <field name="Disable Any MCTR response fix" dword="0" bits="5:5" type="bool" />
+    <field name="Disable Any MCTR response fix Mask" dword="0" bits="21:21" type="bool" />
+  </register>
 </genxml>