From 96ee0d6711ed162b2d3545d7f70927ed35d20c91 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Sat, 30 Mar 2024 02:32:51 +0100 Subject: [PATCH] ac/nir/tess: Remove dead code that was meant for epilogs. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We no longer need to emit store_output intrinsics at the end of the shaders. Signed-off-by: Timur Kristóf Reviewed-by: Marek Olšák Part-of: --- src/amd/common/ac_nir.h | 4 +- src/amd/common/ac_nir_lower_tess_io_to_mem.c | 57 +++----------------- src/amd/vulkan/nir/radv_nir_lower_io.c | 2 +- src/gallium/drivers/radeonsi/si_shader.c | 4 +- 4 files changed, 10 insertions(+), 57 deletions(-) diff --git a/src/amd/common/ac_nir.h b/src/amd/common/ac_nir.h index f9202b53f07..a4617b2e42c 100644 --- a/src/amd/common/ac_nir.h +++ b/src/amd/common/ac_nir.h @@ -129,9 +129,7 @@ ac_nir_lower_hs_outputs_to_mem(nir_shader *shader, unsigned num_reserved_tcs_patch_outputs, unsigned wave_size, bool no_inputs_in_lds, - bool pass_tessfactors_by_reg, - bool emit_tess_factor_write, - bool emit_tess_factor_output); + bool pass_tessfactors_by_reg); void ac_nir_lower_tes_inputs_to_mem(nir_shader *shader, diff --git a/src/amd/common/ac_nir_lower_tess_io_to_mem.c b/src/amd/common/ac_nir_lower_tess_io_to_mem.c index 4d619fef394..79b7b9b918d 100644 --- a/src/amd/common/ac_nir_lower_tess_io_to_mem.c +++ b/src/amd/common/ac_nir_lower_tess_io_to_mem.c @@ -699,15 +699,8 @@ hs_if_invocation_id_zero(nir_builder *b) static void hs_finale(nir_shader *shader, - lower_tess_io_state *st, - bool store_tess_factors, - bool write_tess_factor_outputs) + lower_tess_io_state *st) { - if (!store_tess_factors && !write_tess_factor_outputs) - return; - - assert(!store_tess_factors || !write_tess_factor_outputs); - nir_function_impl *impl = nir_shader_get_entrypoint(shader); assert(impl); nir_block *last_block = nir_impl_last_block(impl); @@ -724,13 +717,10 @@ hs_finale(nir_shader *shader, } /* Only the 1st invocation of each patch needs to access VRAM and/or LDS. */ - nir_if *if_invocation_id_zero = NULL; - if (!st->tcs_pass_tessfactors_by_reg || store_tess_factors) - if_invocation_id_zero = hs_if_invocation_id_zero(b); + nir_if *if_invocation_id_zero = hs_if_invocation_id_zero(b); + { + tess_levels tessfactors = hs_load_tess_levels(b, st); - tess_levels tessfactors = hs_load_tess_levels(b, st); - - if (store_tess_factors) { if (st->gfx_level <= GFX8) hs_store_dynamic_control_word_gfx6(b); @@ -760,38 +750,7 @@ hs_finale(nir_shader *shader, nir_pop_if(b, if_tes_reads_tf); } - if (if_invocation_id_zero) { - /* Make sure that the tess factor definitions are available in top-level CF. */ - nir_push_else(b, if_invocation_id_zero); - nir_def *outer_undef = tessfactors.outer ? nir_undef(b, tessfactors.outer->num_components, 32) : NULL; - nir_def *inner_undef = tessfactors.inner ? nir_undef(b, tessfactors.inner->num_components, 32) : NULL; - nir_pop_if(b, if_invocation_id_zero); - - if (tessfactors.outer) - tessfactors.outer = nir_if_phi(b, tessfactors.outer, outer_undef); - if (tessfactors.inner) - tessfactors.inner = nir_if_phi(b, tessfactors.inner, inner_undef); - } - - if (write_tess_factor_outputs) { - /* Write tess factor output variables, these are passed to the TCS epilog. - * This needs to be in top-level CF, otherwise ACO will have trouble with it - * because nir_lower_io_to_temporaries doesn't work for TCS. - */ - if (st->tcs_tess_level_outer_mask) { - nir_store_output(b, tessfactors.outer, nir_imm_int(b, 0), - .base = st->tcs_tess_level_outer_base, - .write_mask = st->tcs_tess_level_outer_mask, - .io_semantics.location = VARYING_SLOT_TESS_LEVEL_OUTER); - } - - if (st->tcs_tess_level_inner_mask) { - nir_store_output(b, tessfactors.inner, nir_imm_int(b, 0), - .base = st->tcs_tess_level_inner_base, - .write_mask = st->tcs_tess_level_inner_mask, - .io_semantics.location = VARYING_SLOT_TESS_LEVEL_INNER); - } - } + nir_pop_if(b, if_invocation_id_zero); nir_metadata_preserve(impl, nir_metadata_none); } @@ -892,9 +851,7 @@ ac_nir_lower_hs_outputs_to_mem(nir_shader *shader, unsigned num_reserved_tcs_patch_outputs, unsigned wave_size, bool no_inputs_in_lds, - bool pass_tessfactors_by_reg, - bool emit_tess_factor_write, - bool emit_tess_factor_output) + bool pass_tessfactors_by_reg) { assert(shader->info.stage == MESA_SHADER_TESS_CTRL); @@ -923,7 +880,7 @@ ac_nir_lower_hs_outputs_to_mem(nir_shader *shader, lower_hs_output_access, &state); - hs_finale(shader, &state, emit_tess_factor_write, emit_tess_factor_output); + hs_finale(shader, &state); } void diff --git a/src/amd/vulkan/nir/radv_nir_lower_io.c b/src/amd/vulkan/nir/radv_nir_lower_io.c index dc2082f7c18..b581220f9e3 100644 --- a/src/amd/vulkan/nir/radv_nir_lower_io.c +++ b/src/amd/vulkan/nir/radv_nir_lower_io.c @@ -152,7 +152,7 @@ radv_nir_lower_io_to_mem(struct radv_device *device, struct radv_shader_stage *s NIR_PASS_V(nir, ac_nir_lower_hs_inputs_to_mem, map_input, info->vs.tcs_in_out_eq); NIR_PASS_V(nir, ac_nir_lower_hs_outputs_to_mem, map_output, device->physical_device->rad_info.gfx_level, info->tcs.tes_inputs_read, info->tcs.tes_patch_inputs_read, info->tcs.num_linked_outputs, - info->tcs.num_linked_patch_outputs, info->wave_size, false, false, true, false); + info->tcs.num_linked_patch_outputs, info->wave_size, false, false); return true; } else if (nir->info.stage == MESA_SHADER_TESS_EVAL) { diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index 44e9eaaa34a..b938a54471c 100644 --- a/src/gallium/drivers/radeonsi/si_shader.c +++ b/src/gallium/drivers/radeonsi/si_shader.c @@ -1801,9 +1801,7 @@ static bool si_lower_io_to_mem(struct si_shader *shader, nir_shader *nir, /* ALL TCS inputs are passed by register. */ key->ge.opt.same_patch_vertices && !(sel->info.base.inputs_read & ~sel->info.tcs_vgpr_only_inputs), - sel->info.tessfactors_are_def_in_all_invocs, - true, - false); + sel->info.tessfactors_are_def_in_all_invocs); return true; } else if (nir->info.stage == MESA_SHADER_TESS_EVAL) { NIR_PASS_V(nir, ac_nir_lower_tes_inputs_to_mem, si_map_io_driver_location);