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ac,radv,radeonsi: add a function to get the color format endian swap

Browse source 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29265>
This commit is contained in:
Samuel Pitoiset 2024-05-17 14:08:36 +02:00 • committed by Marge Bot
parent 35c6b9c066
commit 96a9625866
6 changed files with 49 additions and 94 deletions
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44
src/amd/common/ac_formats.c
View file

@ -257,6 +257,50 @@ ac_translate_colorswap(enum amd_gfx_level gfx_level, enum pipe_format format, bo
return ~0U;
}
uint32_t
ac_colorformat_endian_swap(uint32_t colorformat)
{
if (UTIL_ARCH_BIG_ENDIAN) {
switch (colorformat) {
/* 8-bit buffers. */
case V_028C70_COLOR_8:
return V_028C70_ENDIAN_NONE;
/* 16-bit buffers. */
case V_028C70_COLOR_5_6_5:
case V_028C70_COLOR_1_5_5_5:
case V_028C70_COLOR_4_4_4_4:
case V_028C70_COLOR_16:
case V_028C70_COLOR_8_8:
return V_028C70_ENDIAN_8IN16;
/* 32-bit buffers. */
case V_028C70_COLOR_8_8_8_8:
case V_028C70_COLOR_2_10_10_10:
case V_028C70_COLOR_10_10_10_2:
case V_028C70_COLOR_8_24:
case V_028C70_COLOR_24_8:
case V_028C70_COLOR_16_16:
return V_028C70_ENDIAN_8IN32;
/* 64-bit buffers. */
case V_028C70_COLOR_16_16_16_16:
return V_028C70_ENDIAN_8IN16;
case V_028C70_COLOR_32_32:
return V_028C70_ENDIAN_8IN32;
/* 128-bit buffers. */
case V_028C70_COLOR_32_32_32_32:
return V_028C70_ENDIAN_8IN32;
default:
return V_028C70_ENDIAN_NONE; /* Unsupported. */
}
} else {
return V_028C70_ENDIAN_NONE;
}
}
uint32_t
ac_translate_dbformat(enum pipe_format format)
{

3
src/amd/common/ac_formats.h
View file

@ -33,6 +33,9 @@ ac_translate_colorswap(enum amd_gfx_level gfx_level,
enum pipe_format format,
bool do_endian_swap);
uint32_t
ac_colorformat_endian_swap(uint32_t colorformat);
uint32_t
ac_translate_dbformat(enum pipe_format format);

2
src/amd/vulkan/radv_device.c
View file

@ -1686,7 +1686,7 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff
assert(format != V_028C70_COLOR_INVALID);
swap = ac_translate_colorswap(pdev->info.gfx_level, vk_format_to_pipe_format(iview->vk.format), false);
endian = radv_colorformat_endian_swap(format);
endian = ac_colorformat_endian_swap(format);
/* blend clamp should be set for all NORM/SRGB types */
if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM || ntype == V_028C70_NUMBER_SRGB)

43
src/amd/vulkan/radv_formats.c
View file

@ -803,49 +803,6 @@ radv_physical_device_get_format_properties(struct radv_physical_device *pdev, Vk
out_properties->bufferFeatures = buffer;
}
uint32_t
radv_colorformat_endian_swap(uint32_t colorformat)
{
if (0 /*UTIL_ARCH_BIG_ENDIAN*/) {
switch (colorformat) {
/* 8-bit buffers. */
case V_028C70_COLOR_8:
return V_028C70_ENDIAN_NONE;
/* 16-bit buffers. */
case V_028C70_COLOR_5_6_5:
case V_028C70_COLOR_1_5_5_5:
case V_028C70_COLOR_4_4_4_4:
case V_028C70_COLOR_16:
case V_028C70_COLOR_8_8:
return V_028C70_ENDIAN_8IN16;
/* 32-bit buffers. */
case V_028C70_COLOR_8_8_8_8:
case V_028C70_COLOR_2_10_10_10:
case V_028C70_COLOR_8_24:
case V_028C70_COLOR_24_8:
case V_028C70_COLOR_16_16:
return V_028C70_ENDIAN_8IN32;
/* 64-bit buffers. */
case V_028C70_COLOR_16_16_16_16:
return V_028C70_ENDIAN_8IN16;
case V_028C70_COLOR_32_32:
return V_028C70_ENDIAN_8IN32;
/* 128-bit buffers. */
case V_028C70_COLOR_32_32_32_32:
return V_028C70_ENDIAN_8IN32;
default:
return V_028C70_ENDIAN_NONE; /* Unsupported. */
}
} else {
return V_028C70_ENDIAN_NONE;
}
}
bool
radv_format_pack_clear_color(VkFormat format, uint32_t clear_vals[2], VkClearColorValue *value)
{

2
src/amd/vulkan/radv_formats.h
View file

@ -159,8 +159,6 @@ bool radv_is_colorbuffer_format_supported(const struct radv_physical_device *pde
bool radv_is_format_emulated(const struct radv_physical_device *pdev, VkFormat format);
uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
bool radv_format_pack_clear_color(VkFormat format, uint32_t clear_vals[2], VkClearColorValue *value);
bool radv_dcc_formats_compatible(enum amd_gfx_level gfx_level, VkFormat format1, VkFormat format2,

49
src/gallium/drivers/radeonsi/si_state.c
View file

@ -1975,53 +1975,6 @@ static void si_emit_db_render_state(struct si_context *sctx, unsigned index)
}
}
/*
* format translation
*/
static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
{
if (UTIL_ARCH_BIG_ENDIAN) {
switch (colorformat) {
/* 8-bit buffers. */
case V_028C70_COLOR_8:
return V_028C70_ENDIAN_NONE;
/* 16-bit buffers. */
case V_028C70_COLOR_5_6_5:
case V_028C70_COLOR_1_5_5_5:
case V_028C70_COLOR_4_4_4_4:
case V_028C70_COLOR_16:
case V_028C70_COLOR_8_8:
return V_028C70_ENDIAN_8IN16;
/* 32-bit buffers. */
case V_028C70_COLOR_8_8_8_8:
case V_028C70_COLOR_2_10_10_10:
case V_028C70_COLOR_10_10_10_2:
case V_028C70_COLOR_8_24:
case V_028C70_COLOR_24_8:
case V_028C70_COLOR_16_16:
return V_028C70_ENDIAN_8IN32;
/* 64-bit buffers. */
case V_028C70_COLOR_16_16_16_16:
return V_028C70_ENDIAN_8IN16;
case V_028C70_COLOR_32_32:
return V_028C70_ENDIAN_8IN32;
/* 128-bit buffers. */
case V_028C70_COLOR_32_32_32_32:
return V_028C70_ENDIAN_8IN32;
default:
return V_028C70_ENDIAN_NONE; /* Unsupported. */
}
} else {
return V_028C70_ENDIAN_NONE;
}
}
/*
* Texture translation
*/
@ -2653,7 +2606,7 @@ static void si_initialize_color_surface(struct si_context *sctx, struct si_surfa
}
assert(format != V_028C70_COLOR_INVALID);
swap = ac_translate_colorswap(sctx->gfx_level, surf->base.format, false);
endian = si_colorformat_endian_swap(format);
endian = ac_colorformat_endian_swap(format);
/* blend clamp should be set for all NORM/SRGB types */
if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||