fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-08 02:38:04 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 4

ac,radv,radeonsi: add a function to translate db format

Browse source 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29265>
This commit is contained in:
Samuel Pitoiset 2024-05-17 14:04:50 +02:00 • committed by Marge Bot
parent 934fc47822
commit 35c6b9c066
6 changed files with 33 additions and 40 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

20
src/amd/common/ac_formats.c
View file

@ -256,3 +256,23 @@ ac_translate_colorswap(enum amd_gfx_level gfx_level, enum pipe_format format, bo
}
return ~0U;
}
uint32_t
ac_translate_dbformat(enum pipe_format format)
{
switch (format) {
case PIPE_FORMAT_Z16_UNORM:
case PIPE_FORMAT_Z16_UNORM_S8_UINT:
return V_028040_Z_16;
case PIPE_FORMAT_S8_UINT_Z24_UNORM:
case PIPE_FORMAT_X8Z24_UNORM:
case PIPE_FORMAT_Z24X8_UNORM:
case PIPE_FORMAT_Z24_UNORM_S8_UINT:
return V_028040_Z_24; /* not present on GFX12 */
case PIPE_FORMAT_Z32_FLOAT:
case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
return V_028040_Z_32_FLOAT;
default:
return V_028040_Z_INVALID;
}
}

3
src/amd/common/ac_formats.h
View file

@ -33,6 +33,9 @@ ac_translate_colorswap(enum amd_gfx_level gfx_level,
enum pipe_format format,
bool do_endian_swap);
uint32_t
ac_translate_dbformat(enum pipe_format format);
#ifdef __cplusplus
}
#endif

2
src/amd/vulkan/radv_device.c
View file

@ -1877,7 +1877,7 @@ radv_initialise_ds_surface(const struct radv_device *device, struct radv_ds_buff
memset(ds, 0, sizeof(*ds));
format = radv_translate_dbformat(vk_format_to_pipe_format(iview->image->vk.format));
format = ac_translate_dbformat(vk_format_to_pipe_format(iview->image->vk.format));
stencil_format = surf->has_stencil ? V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;

21
src/amd/vulkan/radv_formats.c
View file

@ -465,8 +465,10 @@ radv_is_colorbuffer_format_supported(const struct radv_physical_device *pdev, Vk
static bool
radv_is_zs_format_supported(VkFormat format)
{
return radv_translate_dbformat(vk_format_to_pipe_format(format)) != V_028040_Z_INVALID ||
format == VK_FORMAT_S8_UINT;
if (format == VK_FORMAT_D24_UNORM_S8_UINT || format == VK_FORMAT_X8_D24_UNORM_PACK32)
return false;
return ac_translate_dbformat(vk_format_to_pipe_format(format)) != V_028040_Z_INVALID || format == VK_FORMAT_S8_UINT;
}
static bool
@ -844,21 +846,6 @@ radv_colorformat_endian_swap(uint32_t colorformat)
}
}
uint32_t
radv_translate_dbformat(enum pipe_format format)
{
switch (format) {
case PIPE_FORMAT_Z16_UNORM:
case PIPE_FORMAT_Z16_UNORM_S8_UINT:
return V_028040_Z_16;
case PIPE_FORMAT_Z32_FLOAT:
case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
return V_028040_Z_32_FLOAT;
default:
return V_028040_Z_INVALID;
}
}
bool
radv_format_pack_clear_color(VkFormat format, uint32_t clear_vals[2], VkClearColorValue *value)
{

2
src/amd/vulkan/radv_formats.h
View file

@ -161,8 +161,6 @@ bool radv_is_format_emulated(const struct radv_physical_device *pdev, VkFormat f
uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
uint32_t radv_translate_dbformat(enum pipe_format format);
bool radv_format_pack_clear_color(VkFormat format, uint32_t clear_vals[2], VkClearColorValue *value);
bool radv_dcc_formats_compatible(enum amd_gfx_level gfx_level, VkFormat format1, VkFormat format2,

25
src/gallium/drivers/radeonsi/si_state.c
View file

@ -2022,24 +2022,6 @@ static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
}
}
static uint32_t si_translate_dbformat(enum pipe_format format)
{
switch (format) {
case PIPE_FORMAT_Z16_UNORM:
return V_028040_Z_16;
case PIPE_FORMAT_S8_UINT_Z24_UNORM:
case PIPE_FORMAT_X8Z24_UNORM:
case PIPE_FORMAT_Z24X8_UNORM:
case PIPE_FORMAT_Z24_UNORM_S8_UINT:
return V_028040_Z_24; /* not present on GFX12 */
case PIPE_FORMAT_Z32_FLOAT:
case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
return V_028040_Z_32_FLOAT;
default:
return V_028040_Z_INVALID;
}
}
/*
* Texture translation
*/
@ -2530,7 +2512,10 @@ static bool si_is_colorbuffer_format_supported(enum amd_gfx_level gfx_level,
static bool si_is_zs_format_supported(enum pipe_format format)
{
return si_translate_dbformat(format) != V_028040_Z_INVALID;
if (format == PIPE_FORMAT_Z16_UNORM_S8_UINT)
return false;
return ac_translate_dbformat(format) != V_028040_Z_INVALID;
}
static bool si_is_format_supported(struct pipe_screen *screen, enum pipe_format format,
@ -2845,7 +2830,7 @@ static void si_init_depth_surface(struct si_context *sctx, struct si_surface *su
unsigned level = surf->base.u.tex.level;
unsigned format, stencil_format;
format = si_translate_dbformat(tex->db_render_format);
format = ac_translate_dbformat(tex->db_render_format);
stencil_format = tex->surface.has_stencil ? V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
assert(format != V_028040_Z_24 || sctx->gfx_level < GFX12);