From 8fdec3d1612e7db13d2928babb7b1ccd1c5835ee Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= Date: Thu, 6 Apr 2023 10:26:12 -0700 Subject: [PATCH] intel/isl/gfx12.5: Alow hierarchial depth buffer write through for multi sampled surfaces MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Documentation is kinda of ambiguos but at least gfx12.5 is allowed to do hierarchial depth buffer write through for multi sampled surfaces. BSpec: 46965 BSpec: 56419 Suggested-by: Nanley Chery Signed-off-by: José Roberto de Souza Reviewed-by: Francisco Jerez Part-of: --- src/intel/isl/isl.h | 4 ++-- src/intel/isl/isl_emit_depth_stencil.c | 9 +++++---- src/intel/isl/isl_surface_state.c | 4 ++-- 3 files changed, 9 insertions(+), 8 deletions(-) diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h index ecbd316bfee..2b635637049 100644 --- a/src/intel/isl/isl.h +++ b/src/intel/isl/isl.h @@ -827,8 +827,8 @@ enum isl_aux_usage { * CCS-compressed surface contains valid data at all times. * * :invariant: The surface is a color surface - * :invariant: :c:member:`isl_surf.samples` == 1 for GFX 12, GFX 20 can - * be multisampled + * :invariant: :c:member:`isl_surf.samples` == 1 for GFX 12, GFX 12.5 and + * newer can be multisampled */ ISL_AUX_USAGE_HIZ_CCS_WT, diff --git a/src/intel/isl/isl_emit_depth_stencil.c b/src/intel/isl/isl_emit_depth_stencil.c index 856411b1c79..240099a1515 100644 --- a/src/intel/isl/isl_emit_depth_stencil.c +++ b/src/intel/isl/isl_emit_depth_stencil.c @@ -361,12 +361,13 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch, hiz.HierarchicalDepthBufferWriteThruEnable = info->hiz_usage == ISL_AUX_USAGE_HIZ_CCS_WT; -#if GFX_VER == 12 +#if GFX_VERx10 == 120 /* The bspec docs up to GFX 12 for this bit are fairly unclear about * exactly what is and isn't supported with HiZ write-through. It's * fairly clear that you can't sample from a multisampled depth buffer - * with CCS. This limitation isn't called out explicitly but the docs - * for the CCS_E value of RENDER_SURFACE_STATE::AuxiliarySurfaceMode say: + * with CCS on GFX12.0. This limitation isn't called out explicitly but + * the docs for the CCS_E value of + * RENDER_SURFACE_STATE::AuxiliarySurfaceMode say: * * "If Number of multisamples > 1, programming this value means MSAA * compression is enabled for that surface. Auxiliary surface is MSC @@ -393,7 +394,7 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch, */ if (hiz.HierarchicalDepthBufferWriteThruEnable) assert(info->depth_surf->samples == 1); -#endif /* #if GFX_VER == 12 */ +#endif /* #if GFX_VERx10 == 120 */ #endif /* #if GFX_VER >= 12 */ #if GFX_VER >= 8 diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c index 933ed0b0c5e..936885f106d 100644 --- a/src/intel/isl/isl_surface_state.c +++ b/src/intel/isl/isl_surface_state.c @@ -774,12 +774,12 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, * compression, this means that we can't even specify MSAA depth CCS * in RENDER_SURFACE_STATE::AuxiliarySurfaceMode. * - * On Xe2+, the above restriction is not mentioned in the + * On GFX12.5+, the above restriction is not mentioned in the * RENDER_SURFACE_STATE::AuxiliarySurfaceMode. * * Bspec 57023 (r58975) */ - assert(GFX_VER >= 20 || info->surf->samples == 1); + assert(GFX_VERx10 >= 125 || info->surf->samples == 1); /* Prior to Gfx12, the dimension must not be 3D */ if (info->aux_usage == ISL_AUX_USAGE_HIZ)