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nir: assume non-atomic loads don't tear

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Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36602>
This commit is contained in:
Rhys Perry 2025-07-25 16:34:56 +01:00 • committed by Marge Bot
parent 21187c4662
commit 8fba196164
1 changed files with 4 additions and 6 deletions
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10
src/compiler/nir/nir_divergence_analysis.c
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@ -157,17 +157,15 @@ visit_alu(nir_alu_instr *instr, struct divergence_state *state)
* wave can "tear" so that different invocations see the pre-store value and
* the post-store value even though they are loading from the same location.
* This means we have to assume it's not uniform unless it's readonly.
*
* TODO The Vulkan memory model is much more strict here and requires an
* atomic or volatile load for the data race to be valid, which could allow us
* to do better if it's in use, however we currently don't have that
* information plumbed through.
*/
static bool
load_may_tear(struct divergence_state *state, nir_intrinsic_instr *instr)
{
uint32_t access = nir_intrinsic_access(instr);
bool atomic_volatile = access & (ACCESS_ATOMIC | ACCESS_VOLATILE);
return (state->options & nir_divergence_uniform_load_tears) &&
!(nir_intrinsic_access(instr) & ACCESS_NON_WRITEABLE);
!(access & ACCESS_NON_WRITEABLE) &&
(!state->shader->info.assume_no_data_races || atomic_volatile);
}
static bool