From 8fba1961643f8dc6a5dfcc8b295f555a2843943d Mon Sep 17 00:00:00 2001 From: Rhys Perry Date: Fri, 25 Jul 2025 16:34:56 +0100 Subject: [PATCH] nir: assume non-atomic loads don't tear MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Rhys Perry Reviewed-by: Daniel Schürmann Reviewed-by: Georg Lehmann Reviewed-by: Faith Ekstrand Part-of: --- src/compiler/nir/nir_divergence_analysis.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/src/compiler/nir/nir_divergence_analysis.c b/src/compiler/nir/nir_divergence_analysis.c index c3785f61e22..15ba95f52ff 100644 --- a/src/compiler/nir/nir_divergence_analysis.c +++ b/src/compiler/nir/nir_divergence_analysis.c @@ -157,17 +157,15 @@ visit_alu(nir_alu_instr *instr, struct divergence_state *state) * wave can "tear" so that different invocations see the pre-store value and * the post-store value even though they are loading from the same location. * This means we have to assume it's not uniform unless it's readonly. - * - * TODO The Vulkan memory model is much more strict here and requires an - * atomic or volatile load for the data race to be valid, which could allow us - * to do better if it's in use, however we currently don't have that - * information plumbed through. */ static bool load_may_tear(struct divergence_state *state, nir_intrinsic_instr *instr) { + uint32_t access = nir_intrinsic_access(instr); + bool atomic_volatile = access & (ACCESS_ATOMIC | ACCESS_VOLATILE); return (state->options & nir_divergence_uniform_load_tears) && - !(nir_intrinsic_access(instr) & ACCESS_NON_WRITEABLE); + !(access & ACCESS_NON_WRITEABLE) && + (!state->shader->info.assume_no_data_races || atomic_volatile); } static bool