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anv: add depth, DC and L3 fabric flush for aux map invalidation

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These should be included according to table in Bspec 43904.

Patch removes PIPE_CONTROL_STATE_CACHE_INVALIDATE based on HSDES.

Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29764>
(cherry picked from commit 78b614b333)
This commit is contained in:
Tapani Pälli 2024-10-02 12:49:51 +03:00 • committed by Eric Engestrom
parent 21781fb360
commit 8d3fc29b38
2 changed files with 22 additions and 22 deletions
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2
.pick_status.json
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@ -4,7 +4,7 @@
"description": "anv: add depth, DC and L3 fabric flush for aux map invalidation",
"nominated": true,
"nomination_type": 0,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": null,
"notes": null

42
src/intel/vulkan/genX_cmd_buffer.c
View file

@ -1666,37 +1666,37 @@ genX(emit_apply_pipe_flushes)(struct anv_batch *batch,
if (bits & ANV_PIPE_FLUSH_BITS)
bits |= ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT;
/* HSD 1209978178: docs say that before programming the aux table:
/* From Bspec 43904 (Register_CCSAuxiliaryTableInvalidate):
* RCS engine idle sequence:
*
* "Driver must ensure that the engine is IDLE but ensure it doesn't
* add extra flushes in the case it knows that the engine is already
* IDLE."
* Gfx12+:
* PIPE_CONTROL:- DC Flush + L3 Fabric Flush + CS Stall + Render
* Target Cache Flush + Depth Cache
*
* HSD 22012751911: SW Programming sequence when issuing aux invalidation:
* Gfx125+:
* PIPE_CONTROL:- DC Flush + L3 Fabric Flush + CS Stall + Render
* Target Cache Flush + Depth Cache + CCS flush
*
* "Render target Cache Flush + L3 Fabric Flush + State Invalidation + CS Stall"
* Compute engine idle sequence:
*
* Notice we don't set the L3 Fabric Flush here, because we have
* ANV_PIPE_END_OF_PIPE_SYNC_BIT which inserts a CS stall. The
* PIPE_CONTROL::L3 Fabric Flush documentation says :
* Gfx12+:
* PIPE_CONTROL:- DC Flush + L3 Fabric Flush + CS Stall
*
* "L3 Fabric Flush will ensure all the pending transactions in the L3
* Fabric are flushed to global observation point. HW does implicit L3
* Fabric Flush on all stalling flushes (both explicit and implicit)
* and on PIPECONTROL having Post Sync Operation enabled."
*
* Therefore setting L3 Fabric Flush here would be redundant.
* Gfx125+:
* PIPE_CONTROL:- DC Flush + L3 Fabric Flush + CS Stall + CCS flush
*/
if (GFX_VER == 12 && (bits & ANV_PIPE_AUX_TABLE_INVALIDATE_BIT)) {
if (current_pipeline == GPGPU) {
bits |= (ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT |
ANV_PIPE_DATA_CACHE_FLUSH_BIT |
(GFX_VERx10 == 125 ? ANV_PIPE_CCS_CACHE_FLUSH_BIT: 0));
bits |= (ANV_PIPE_DATA_CACHE_FLUSH_BIT |
ANV_PIPE_L3_FABRIC_FLUSH_BIT |
ANV_PIPE_CS_STALL_BIT |
(GFX_VERx10 == 125 ? ANV_PIPE_CCS_CACHE_FLUSH_BIT: 0));
} else if (current_pipeline == _3D) {
bits |= (ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT |
bits |= (ANV_PIPE_DATA_CACHE_FLUSH_BIT |
ANV_PIPE_L3_FABRIC_FLUSH_BIT |
ANV_PIPE_CS_STALL_BIT |
ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT |
ANV_PIPE_STATE_CACHE_INVALIDATE_BIT |
ANV_PIPE_DEPTH_CACHE_FLUSH_BIT |
(GFX_VERx10 == 125 ? ANV_PIPE_CCS_CACHE_FLUSH_BIT: 0));
}
}