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iris: add depth, DC and L3 fabric flush for aux map invalidation

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These should be included according to table in Bspec 43904.

Patch removes PIPE_CONTROL_STATE_CACHE_INVALIDATE based on HSDES.

Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29764>
(cherry picked from commit 3e29ea69ce)
This commit is contained in:
Tapani Pälli 2024-06-18 12:08:01 +03:00 • committed by Eric Engestrom
parent 28691fb5d1
commit 21781fb360
2 changed files with 14 additions and 43 deletions
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2
.pick_status.json
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@ -14,7 +14,7 @@
"description": "iris: add depth, DC and L3 fabric flush for aux map invalidation",
"nominated": true,
"nomination_type": 0,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": null,
"notes": null

55
src/gallium/drivers/iris/iris_state.c
View file

@ -6141,43 +6141,23 @@ invalidate_aux_map_state_per_engine(struct iris_batch *batch)
switch (batch->name) {
case IRIS_BATCH_RENDER: {
/* HSD 1209978178: docs say that before programming the aux table:
*
* "Driver must ensure that the engine is IDLE but ensure it doesn't
* add extra flushes in the case it knows that the engine is already
* IDLE."
*
* An end of pipe sync is needed here, otherwise we see GPU hangs in
* dEQP-GLES31.functional.copy_image.* tests.
*
* HSD 22012751911: SW Programming sequence when issuing aux invalidation:
*
* "Render target Cache Flush + L3 Fabric Flush + State Invalidation + CS Stall"
*
* Notice we don't set the L3 Fabric Flush here, because we have
* PIPE_CONTROL_CS_STALL. The PIPE_CONTROL::L3 Fabric Flush
* documentation says :
*
* "L3 Fabric Flush will ensure all the pending transactions in the
* L3 Fabric are flushed to global observation point. HW does
* implicit L3 Fabric Flush on all stalling flushes (both explicit
* and implicit) and on PIPECONTROL having Post Sync Operation
* enabled."
*
* Therefore setting L3 Fabric Flush here would be redundant.
*
* From Bspec 43904 (Register_CCSAuxiliaryTableInvalidate):
/* From Bspec 43904 (Register_CCSAuxiliaryTableInvalidate):
* RCS engine idle sequence:
*
* Gfx12+:
* PIPE_CONTROL:- DC Flush + L3 Fabric Flush + CS Stall + Render
* Target Cache Flush + Depth Cache
*
* Gfx125+:
* PIPE_CONTROL:- DC Flush + L3 Fabric Flush + CS Stall + Render
* Target Cache Flush + Depth Cache + CCS flush
*
*/
iris_emit_end_of_pipe_sync(batch, "Invalidate aux map table",
PIPE_CONTROL_DATA_CACHE_FLUSH |
PIPE_CONTROL_L3_FABRIC_FLUSH |
PIPE_CONTROL_CS_STALL |
PIPE_CONTROL_RENDER_TARGET_FLUSH |
PIPE_CONTROL_STATE_CACHE_INVALIDATE |
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
(GFX_VERx10 == 125 ?
PIPE_CONTROL_CCS_CACHE_FLUSH : 0));
@ -6185,27 +6165,18 @@ invalidate_aux_map_state_per_engine(struct iris_batch *batch)
break;
}
case IRIS_BATCH_COMPUTE: {
/*
* Notice we don't set the L3 Fabric Flush here, because we have
* PIPE_CONTROL_CS_STALL. The PIPE_CONTROL::L3 Fabric Flush
* documentation says :
*
* "L3 Fabric Flush will ensure all the pending transactions in the
* L3 Fabric are flushed to global observation point. HW does
* implicit L3 Fabric Flush on all stalling flushes (both explicit
* and implicit) and on PIPECONTROL having Post Sync Operation
* enabled."
*
* Therefore setting L3 Fabric Flush here would be redundant.
*
* From Bspec 43904 (Register_CCSAuxiliaryTableInvalidate):
/* From Bspec 43904 (Register_CCSAuxiliaryTableInvalidate):
* Compute engine idle sequence:
*
* Gfx12+:
* PIPE_CONTROL:- DC Flush + L3 Fabric Flush + CS Stall
*
* Gfx125+:
* PIPE_CONTROL:- DC Flush + L3 Fabric Flush + CS Stall + CCS flush
*/
iris_emit_end_of_pipe_sync(batch, "Invalidate aux map table",
PIPE_CONTROL_DATA_CACHE_FLUSH |
PIPE_CONTROL_L3_FABRIC_FLUSH |
PIPE_CONTROL_CS_STALL |
(GFX_VERx10 == 125 ?
PIPE_CONTROL_CCS_CACHE_FLUSH : 0));