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intel/compiler: Drop redundant 32-bit expansion for shared float atomics

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We already expanded data to 32-bit a few lines earlier, so this is just
redundantly doing it a second time.

Fixes: 43169dbbe5 ("intel/compiler: Support 16 bit float ops")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20604>
(cherry picked from commit f7b29d7924)
This commit is contained in:
Kenneth Graunke 2023-01-09 15:57:14 -08:00 • committed by Eric Engestrom
parent 7fe1d202d5
commit 89e679803b
2 changed files with 2 additions and 2 deletions
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2
.pick_status.json
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@ -3010,7 +3010,7 @@
"description": "intel/compiler: Drop redundant 32-bit expansion for shared float atomics",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": "43169dbbe5f963ca47d51873f6639fbe3fd665b0"
},

2
src/intel/compiler/brw_fs_nir.cpp
View file

@ -6109,7 +6109,7 @@ fs_visitor::nir_emit_shared_atomic(const fs_builder &bld,
if (op == BRW_AOP_CMPWR) {
fs_reg tmp = bld.vgrf(data.type, 2);
fs_reg sources[2] = {
expand_to_32bit(bld, data),
data,
expand_to_32bit(bld, get_nir_src(instr->src[2]))
};
bld.LOAD_PAYLOAD(tmp, sources, 2, 0);