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i965/gen10: Implement Wa3DStateMode

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This workaround doesn't fix any of the piglit hangs we've seen
on CNL. But it might be fixing something we haven't tested yet.

V2: Remove the bits enabling Float blend optimization. It is
    enabled through CACHE_MODE_SS register.
    Update the comment.
    Move gen10 if block on top of gen9 if block.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
This commit is contained in:
Anuj Phogat 2017-09-12 16:05:06 -07:00
parent 6c681b4cc1
commit 898e5555de
2 changed files with 16 additions and 0 deletions
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2
src/mesa/drivers/dri/i965/brw_defines.h
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@ -1333,6 +1333,8 @@ enum brw_pixel_shader_coverage_mask_mode {
/* DW2: start address */
/* DW3: end address. */
#define _3DSTATE_3D_MODE 0x791e
#define CMD_MI_FLUSH 0x0200
# define BLT_X_SHIFT 0

14
src/mesa/drivers/dri/i965/brw_state_upload.c
View file

@ -66,6 +66,20 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
brw_load_register_imm32(brw, GEN10_CACHE_MODE_SS,
REG_MASK(GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE) |
GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE);
/* From gen10 workaround table in h/w specs:
*
* "On 3DSTATE_3D_MODE, driver must always program bits 31:16 of DW1
* a value of 0xFFFF"
*
* This means that we end up setting the entire 3D_MODE state. Bits
* in this register control things such as slice hashing and we want
* the default values of zero at the moment.
*/
BEGIN_BATCH(2);
OUT_BATCH(_3DSTATE_3D_MODE << 16 | (2 - 2));
OUT_BATCH(0xFFFF << 16);
ADVANCE_BATCH();
}
if (devinfo->gen == 9) {