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i965/gen10: Enable float blend optimization

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This optimization is enabled for previous generations too.
See Mesa commit c17e214a6b
On CNL this bit has been moved to CACHE_MODE_SS register.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
This commit is contained in:
Anuj Phogat 2017-10-31 09:28:09 -07:00
parent d3d0fe4572
commit 6c681b4cc1
2 changed files with 9 additions and 0 deletions
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3
src/mesa/drivers/dri/i965/brw_defines.h
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@ -1688,6 +1688,9 @@ enum brw_pixel_shader_coverage_mask_mode {
# define GEN8_L3CNTLREG_ALL_ALLOC_SHIFT 25
# define GEN8_L3CNTLREG_ALL_ALLOC_MASK INTEL_MASK(31, 25)
#define GEN10_CACHE_MODE_SS 0x0e420
#define GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4)
#define INSTPM 0x20c0
# define INSTPM_CONSTANT_BUFFER_ADDRESS_OFFSET_DISABLE (1 << 6)

6
src/mesa/drivers/dri/i965/brw_state_upload.c
View file

@ -62,6 +62,12 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
brw_upload_invariant_state(brw);
if (devinfo->gen == 10) {
brw_load_register_imm32(brw, GEN10_CACHE_MODE_SS,
REG_MASK(GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE) |
GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE);
}
if (devinfo->gen == 9) {
/* Recommended optimizations for Victim Cache eviction and floating
* point blending.