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pvr: Use common pipeline & dynamic state frameworks

Browse source 
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19342>
This commit is contained in:
Matt Coster 2022-09-05 15:47:31 +01:00 • committed by Marge Bot
parent a89ff8d4bc
commit 88f1fad3f7
3 changed files with 393 additions and 731 deletions
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681
src/imagination/vulkan/pvr_cmd_buffer.c
View file

File diff suppressed because it is too large Load diff

305
src/imagination/vulkan/pvr_pipeline.c
View file

@ -48,8 +48,10 @@
#include "util/ralloc.h"
#include "util/u_math.h"
#include "vk_alloc.h"
#include "vk_graphics_state.h"
#include "vk_log.h"
#include "vk_object.h"
#include "vk_render_pass.h"
#include "vk_util.h"
/*****************************************************************************
@ -1299,62 +1301,38 @@ pvr_CreateComputePipelines(VkDevice _device,
Graphics pipeline functions
******************************************************************************/
static inline uint32_t pvr_dynamic_state_bit_from_vk(VkDynamicState state)
{
switch (state) {
case VK_DYNAMIC_STATE_VIEWPORT:
return PVR_DYNAMIC_STATE_BIT_VIEWPORT;
case VK_DYNAMIC_STATE_SCISSOR:
return PVR_DYNAMIC_STATE_BIT_SCISSOR;
case VK_DYNAMIC_STATE_LINE_WIDTH:
return PVR_DYNAMIC_STATE_BIT_LINE_WIDTH;
case VK_DYNAMIC_STATE_DEPTH_BIAS:
return PVR_DYNAMIC_STATE_BIT_DEPTH_BIAS;
case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
return PVR_DYNAMIC_STATE_BIT_BLEND_CONSTANTS;
case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
return PVR_DYNAMIC_STATE_BIT_STENCIL_COMPARE_MASK;
case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
return PVR_DYNAMIC_STATE_BIT_STENCIL_WRITE_MASK;
case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
return PVR_DYNAMIC_STATE_BIT_STENCIL_REFERENCE;
default:
unreachable("Unsupported state.");
}
}
static void
pvr_graphics_pipeline_destroy(struct pvr_device *const device,
const VkAllocationCallbacks *const allocator,
struct pvr_graphics_pipeline *const gfx_pipeline)
{
const uint32_t num_vertex_attrib_programs =
ARRAY_SIZE(gfx_pipeline->vertex_shader_state.pds_attrib_programs);
ARRAY_SIZE(gfx_pipeline->shader_state.vertex.pds_attrib_programs);
pvr_pds_descriptor_program_destroy(
device,
allocator,
&gfx_pipeline->fragment_shader_state.descriptor_state);
&gfx_pipeline->shader_state.fragment.descriptor_state);
pvr_pds_descriptor_program_destroy(
device,
allocator,
&gfx_pipeline->vertex_shader_state.descriptor_state);
&gfx_pipeline->shader_state.vertex.descriptor_state);
for (uint32_t i = 0; i < num_vertex_attrib_programs; i++) {
struct pvr_pds_attrib_program *const attrib_program =
&gfx_pipeline->vertex_shader_state.pds_attrib_programs[i];
&gfx_pipeline->shader_state.vertex.pds_attrib_programs[i];
pvr_pds_vertex_attrib_program_destroy(device, allocator, attrib_program);
}
pvr_bo_free(device,
gfx_pipeline->fragment_shader_state.pds_fragment_program.pvr_bo);
gfx_pipeline->shader_state.fragment.pds_fragment_program.pvr_bo);
pvr_bo_free(device,
gfx_pipeline->fragment_shader_state.pds_coeff_program.pvr_bo);
gfx_pipeline->shader_state.fragment.pds_coeff_program.pvr_bo);
pvr_bo_free(device, gfx_pipeline->fragment_shader_state.bo);
pvr_bo_free(device, gfx_pipeline->vertex_shader_state.bo);
pvr_bo_free(device, gfx_pipeline->shader_state.fragment.bo);
pvr_bo_free(device, gfx_pipeline->shader_state.vertex.bo);
pvr_pipeline_finish(&gfx_pipeline->base);
@ -1367,7 +1345,7 @@ pvr_vertex_state_init(struct pvr_graphics_pipeline *gfx_pipeline,
const struct rogue_vs_build_data *vs_data)
{
struct pvr_vertex_shader_state *vertex_state =
&gfx_pipeline->vertex_shader_state;
&gfx_pipeline->shader_state.vertex;
/* TODO: Hard coding these for now. These should be populated based on the
* information returned by the compiler.
@ -1392,7 +1370,7 @@ pvr_vertex_state_init(struct pvr_graphics_pipeline *gfx_pipeline,
* shader inputs and assigned in the place where that happens.
* There will also be an opportunity to cull unused fs inputs/vs outputs.
*/
pvr_csb_pack (&gfx_pipeline->vertex_shader_state.varying[0],
pvr_csb_pack (&gfx_pipeline->shader_state.vertex.varying[0],
TA_STATE_VARYING0,
varying0) {
varying0.f32_linear = vs_data->num_varyings;
@ -1400,7 +1378,7 @@ pvr_vertex_state_init(struct pvr_graphics_pipeline *gfx_pipeline,
varying0.f32_npc = 0;
}
pvr_csb_pack (&gfx_pipeline->vertex_shader_state.varying[1],
pvr_csb_pack (&gfx_pipeline->shader_state.vertex.varying[1],
TA_STATE_VARYING1,
varying1) {
varying1.f16_linear = 0;
@ -1414,7 +1392,7 @@ pvr_fragment_state_init(struct pvr_graphics_pipeline *gfx_pipeline,
const struct rogue_common_build_data *common_data)
{
struct pvr_fragment_shader_state *fragment_state =
&gfx_pipeline->fragment_shader_state;
&gfx_pipeline->shader_state.fragment;
/* TODO: Hard coding these for now. These should be populated based on the
* information returned by the compiler.
@ -1555,7 +1533,7 @@ pvr_graphics_pipeline_compile(struct pvr_device *const device,
BITFIELD_BIT(MESA_SHADER_VERTEX)) {
pvr_hard_code_graphics_vertex_state(&device->pdevice->dev_info,
hard_code_pipeline_n,
&gfx_pipeline->vertex_shader_state);
&gfx_pipeline->shader_state.vertex);
} else {
pvr_vertex_state_init(gfx_pipeline,
&ctx->common_data[MESA_SHADER_VERTEX],
@ -1566,7 +1544,7 @@ pvr_graphics_pipeline_compile(struct pvr_device *const device,
ctx->binary[MESA_SHADER_VERTEX]->data,
ctx->binary[MESA_SHADER_VERTEX]->size,
cache_line_size,
&gfx_pipeline->vertex_shader_state.bo);
&gfx_pipeline->shader_state.vertex.bo);
if (result != VK_SUCCESS)
goto err_free_build_context;
@ -1576,7 +1554,7 @@ pvr_graphics_pipeline_compile(struct pvr_device *const device,
pvr_hard_code_graphics_fragment_state(
&device->pdevice->dev_info,
hard_code_pipeline_n,
&gfx_pipeline->fragment_shader_state);
&gfx_pipeline->shader_state.fragment);
} else {
pvr_fragment_state_init(gfx_pipeline,
&ctx->common_data[MESA_SHADER_FRAGMENT]);
@ -1586,7 +1564,7 @@ pvr_graphics_pipeline_compile(struct pvr_device *const device,
ctx->binary[MESA_SHADER_FRAGMENT]->data,
ctx->binary[MESA_SHADER_FRAGMENT]->size,
cache_line_size,
&gfx_pipeline->fragment_shader_state.bo);
&gfx_pipeline->shader_state.fragment.bo);
if (result != VK_SUCCESS)
goto err_free_vertex_bo;
@ -1601,18 +1579,18 @@ pvr_graphics_pipeline_compile(struct pvr_device *const device,
ctx->stage_data.fs.iterator_args.fpu_iterators,
ctx->stage_data.fs.iterator_args.num_fpu_iterators,
ctx->stage_data.fs.iterator_args.destination,
&gfx_pipeline->fragment_shader_state.pds_coeff_program);
&gfx_pipeline->shader_state.fragment.pds_coeff_program);
if (result != VK_SUCCESS)
goto err_free_fragment_bo;
result = pvr_pds_fragment_program_create_and_upload(
device,
allocator,
gfx_pipeline->fragment_shader_state.bo,
gfx_pipeline->shader_state.fragment.bo,
ctx->common_data[MESA_SHADER_FRAGMENT].temps,
ctx->stage_data.fs.msaa_mode,
ctx->stage_data.fs.phas,
&gfx_pipeline->fragment_shader_state.pds_fragment_program);
&gfx_pipeline->shader_state.fragment.pds_fragment_program);
if (result != VK_SUCCESS)
goto err_free_coeff_program;
@ -1622,7 +1600,7 @@ pvr_graphics_pipeline_compile(struct pvr_device *const device,
vertex_input_state,
ctx->common_data[MESA_SHADER_VERTEX].temps,
&ctx->stage_data.vs,
&gfx_pipeline->vertex_shader_state.pds_attrib_programs);
&gfx_pipeline->shader_state.vertex.pds_attrib_programs);
if (result != VK_SUCCESS)
goto err_free_frag_program;
@ -1634,7 +1612,7 @@ pvr_graphics_pipeline_compile(struct pvr_device *const device,
&vert_explicit_const_usage,
gfx_pipeline->base.layout,
PVR_STAGE_ALLOCATION_VERTEX_GEOMETRY,
&gfx_pipeline->vertex_shader_state.descriptor_state);
&gfx_pipeline->shader_state.vertex.descriptor_state);
if (result != VK_SUCCESS)
goto err_free_vertex_attrib_program;
@ -1656,7 +1634,7 @@ pvr_graphics_pipeline_compile(struct pvr_device *const device,
&frag_explicit_const_usage,
gfx_pipeline->base.layout,
PVR_STAGE_ALLOCATION_FRAGMENT,
&gfx_pipeline->fragment_shader_state.descriptor_state);
&gfx_pipeline->shader_state.fragment.descriptor_state);
if (result != VK_SUCCESS)
goto err_free_vertex_descriptor_program;
@ -1670,157 +1648,60 @@ err_free_vertex_descriptor_program:
pvr_pds_descriptor_program_destroy(
device,
allocator,
&gfx_pipeline->vertex_shader_state.descriptor_state);
&gfx_pipeline->shader_state.vertex.descriptor_state);
err_free_vertex_attrib_program:
for (uint32_t i = 0;
i < ARRAY_SIZE(gfx_pipeline->vertex_shader_state.pds_attrib_programs);
i < ARRAY_SIZE(gfx_pipeline->shader_state.vertex.pds_attrib_programs);
i++) {
struct pvr_pds_attrib_program *const attrib_program =
&gfx_pipeline->vertex_shader_state.pds_attrib_programs[i];
&gfx_pipeline->shader_state.vertex.pds_attrib_programs[i];
pvr_pds_vertex_attrib_program_destroy(device, allocator, attrib_program);
}
err_free_frag_program:
pvr_bo_free(device,
gfx_pipeline->fragment_shader_state.pds_fragment_program.pvr_bo);
gfx_pipeline->shader_state.fragment.pds_fragment_program.pvr_bo);
err_free_coeff_program:
pvr_bo_free(device,
gfx_pipeline->fragment_shader_state.pds_coeff_program.pvr_bo);
gfx_pipeline->shader_state.fragment.pds_coeff_program.pvr_bo);
err_free_fragment_bo:
pvr_bo_free(device, gfx_pipeline->fragment_shader_state.bo);
pvr_bo_free(device, gfx_pipeline->shader_state.fragment.bo);
err_free_vertex_bo:
pvr_bo_free(device, gfx_pipeline->vertex_shader_state.bo);
pvr_bo_free(device, gfx_pipeline->shader_state.vertex.bo);
err_free_build_context:
ralloc_free(ctx);
return result;
}
static void pvr_graphics_pipeline_init_depth_and_stencil_state(
struct pvr_graphics_pipeline *gfx_pipeline,
const VkPipelineDepthStencilStateCreateInfo *depth_stencil_state)
static struct vk_subpass_info
pvr_create_subpass_info(const VkGraphicsPipelineCreateInfo *const info)
{
const VkStencilOpState *front;
const VkStencilOpState *back;
PVR_FROM_HANDLE(pvr_render_pass, pass, info->renderPass);
const struct pvr_render_subpass *const subpass =
&pass->subpasses[info->subpass];
if (!depth_stencil_state)
return;
VkImageAspectFlags attachment_aspects = VK_IMAGE_ASPECT_NONE;
front = &depth_stencil_state->front;
back = &depth_stencil_state->back;
assert(info->subpass < pass->subpass_count);
if (depth_stencil_state->depthTestEnable) {
gfx_pipeline->depth_compare_op = depth_stencil_state->depthCompareOp;
gfx_pipeline->depth_write_disable =
!depth_stencil_state->depthWriteEnable;
} else {
gfx_pipeline->depth_compare_op = VK_COMPARE_OP_ALWAYS;
gfx_pipeline->depth_write_disable = true;
for (uint32_t i = 0; i < subpass->color_count; i++) {
attachment_aspects |=
pass->attachments[subpass->color_attachments[i]].aspects;
}
if (depth_stencil_state->stencilTestEnable) {
gfx_pipeline->stencil_front.compare_op = front->compareOp;
gfx_pipeline->stencil_front.fail_op = front->failOp;
gfx_pipeline->stencil_front.depth_fail_op = front->depthFailOp;
gfx_pipeline->stencil_front.pass_op = front->passOp;
gfx_pipeline->stencil_back.compare_op = back->compareOp;
gfx_pipeline->stencil_back.fail_op = back->failOp;
gfx_pipeline->stencil_back.depth_fail_op = back->depthFailOp;
gfx_pipeline->stencil_back.pass_op = back->passOp;
} else {
gfx_pipeline->stencil_front.compare_op = VK_COMPARE_OP_ALWAYS;
gfx_pipeline->stencil_front.fail_op = VK_STENCIL_OP_KEEP;
gfx_pipeline->stencil_front.depth_fail_op = VK_STENCIL_OP_KEEP;
gfx_pipeline->stencil_front.pass_op = VK_STENCIL_OP_KEEP;
gfx_pipeline->stencil_back = gfx_pipeline->stencil_front;
}
}
static void pvr_graphics_pipeline_init_dynamic_state(
struct pvr_graphics_pipeline *gfx_pipeline,
const VkPipelineDynamicStateCreateInfo *dynamic_state,
const VkPipelineViewportStateCreateInfo *viewport_state,
const VkPipelineDepthStencilStateCreateInfo *depth_stencil_state,
const VkPipelineColorBlendStateCreateInfo *color_blend_state,
const VkPipelineRasterizationStateCreateInfo *rasterization_state)
{
struct pvr_dynamic_state *const internal_dynamic_state =
&gfx_pipeline->dynamic_state;
uint32_t dynamic_states = 0;
if (dynamic_state) {
for (uint32_t i = 0; i < dynamic_state->dynamicStateCount; i++) {
dynamic_states |=
pvr_dynamic_state_bit_from_vk(dynamic_state->pDynamicStates[i]);
}
if (subpass->depth_stencil_attachment) {
attachment_aspects |=
pass->attachments[*subpass->depth_stencil_attachment].aspects;
}
/* TODO: Verify this.
* We don't zero out the pipeline's state if they are dynamic since they
* should be set later on in the command buffer.
*/
return (struct vk_subpass_info){
.attachment_aspects = attachment_aspects,
/* TODO: Handle rasterizerDiscardEnable. */
if (rasterization_state) {
if (!(dynamic_states & PVR_DYNAMIC_STATE_BIT_LINE_WIDTH))
internal_dynamic_state->line_width = rasterization_state->lineWidth;
/* TODO: Do we need the depthBiasEnable check? */
if (!(dynamic_states & PVR_DYNAMIC_STATE_BIT_DEPTH_BIAS)) {
internal_dynamic_state->depth_bias = (struct pvr_depth_bias_state){
.constant_factor = rasterization_state->depthBiasConstantFactor,
.slope_factor = rasterization_state->depthBiasSlopeFactor,
.clamp = rasterization_state->depthBiasClamp,
};
}
}
/* TODO: handle viewport state flags. */
/* TODO: handle static viewport state. */
/* We assume the viewport state to by dynamic for now. */
/* TODO: handle static scissor state. */
/* We assume the scissor state to by dynamic for now. */
if (depth_stencil_state) {
const VkStencilOpState *const front = &depth_stencil_state->front;
const VkStencilOpState *const back = &depth_stencil_state->back;
/* VkPhysicalDeviceFeatures->depthBounds is false. */
assert(depth_stencil_state->depthBoundsTestEnable == VK_FALSE);
if (!(dynamic_states & PVR_DYNAMIC_STATE_BIT_STENCIL_COMPARE_MASK)) {
internal_dynamic_state->compare_mask.front = front->compareMask;
internal_dynamic_state->compare_mask.back = back->compareMask;
}
if (!(dynamic_states & PVR_DYNAMIC_STATE_BIT_STENCIL_WRITE_MASK)) {
internal_dynamic_state->write_mask.front = front->writeMask;
internal_dynamic_state->write_mask.back = back->writeMask;
}
if (!(dynamic_states & PVR_DYNAMIC_STATE_BIT_STENCIL_REFERENCE)) {
internal_dynamic_state->reference.front = front->reference;
internal_dynamic_state->reference.back = back->reference;
}
}
if (color_blend_state &&
!(dynamic_states & PVR_DYNAMIC_STATE_BIT_BLEND_CONSTANTS)) {
STATIC_ASSERT(__same_type(internal_dynamic_state->blend_constants,
color_blend_state->blendConstants));
typed_memcpy(internal_dynamic_state->blend_constants,
color_blend_state->blendConstants,
ARRAY_SIZE(internal_dynamic_state->blend_constants));
}
/* TODO: handle STATIC_STATE_DEPTH_BOUNDS ? */
internal_dynamic_state->mask = dynamic_states;
/* TODO: This is only needed for VK_KHR_create_renderpass2 (or core 1.2),
* which is not currently supported.
*/
.view_mask = 0,
};
}
static VkResult
@ -1830,51 +1711,39 @@ pvr_graphics_pipeline_init(struct pvr_device *device,
const VkAllocationCallbacks *allocator,
struct pvr_graphics_pipeline *gfx_pipeline)
{
/* If rasterization is not enabled, various CreateInfo structs must be
* ignored.
*/
const bool raster_discard_enabled =
pCreateInfo->pRasterizationState->rasterizerDiscardEnable;
const VkPipelineViewportStateCreateInfo *vs_info =
!raster_discard_enabled ? pCreateInfo->pViewportState : NULL;
const VkPipelineDepthStencilStateCreateInfo *dss_info =
!raster_discard_enabled ? pCreateInfo->pDepthStencilState : NULL;
const VkPipelineRasterizationStateCreateInfo *rs_info =
!raster_discard_enabled ? pCreateInfo->pRasterizationState : NULL;
const VkPipelineColorBlendStateCreateInfo *cbs_info =
!raster_discard_enabled ? pCreateInfo->pColorBlendState : NULL;
const VkPipelineMultisampleStateCreateInfo *ms_info =
!raster_discard_enabled ? pCreateInfo->pMultisampleState : NULL;
struct vk_dynamic_graphics_state *const dynamic_state =
&gfx_pipeline->dynamic_state;
const struct vk_subpass_info sp_info = pvr_create_subpass_info(pCreateInfo);
struct vk_graphics_pipeline_all_state all_state;
struct vk_graphics_pipeline_state state = { 0 };
VkResult result;
pvr_pipeline_init(device, PVR_PIPELINE_TYPE_GRAPHICS, &gfx_pipeline->base);
gfx_pipeline->raster_state.discard_enable = raster_discard_enabled;
gfx_pipeline->raster_state.cull_mode =
pCreateInfo->pRasterizationState->cullMode;
gfx_pipeline->raster_state.front_face =
pCreateInfo->pRasterizationState->frontFace;
gfx_pipeline->raster_state.depth_bias_enable =
pCreateInfo->pRasterizationState->depthBiasEnable;
gfx_pipeline->raster_state.depth_clamp_enable =
pCreateInfo->pRasterizationState->depthClampEnable;
result = vk_graphics_pipeline_state_fill(&device->vk,
&state,
pCreateInfo,
&sp_info,
&all_state,
NULL,
0,
NULL);
if (result != VK_SUCCESS)
goto err_pipeline_finish;
/* FIXME: Handle depthClampEnable. */
vk_dynamic_graphics_state_init(dynamic_state);
pvr_graphics_pipeline_init_depth_and_stencil_state(gfx_pipeline, dss_info);
pvr_graphics_pipeline_init_dynamic_state(gfx_pipeline,
pCreateInfo->pDynamicState,
vs_info,
dss_info,
cbs_info,
rs_info);
/* Load static state into base dynamic state holder. */
vk_dynamic_graphics_state_fill(dynamic_state, &state);
if (pCreateInfo->pInputAssemblyState) {
gfx_pipeline->input_asm_state.topology =
pCreateInfo->pInputAssemblyState->topology;
gfx_pipeline->input_asm_state.primitive_restart =
pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
}
/* The value of ms.rasterization_samples is undefined when
* rasterizer_discard_enable is set, but we need a specific value.
* Fill that in here.
*/
if (state.rs->rasterizer_discard_enable)
dynamic_state->ms.rasterization_samples = VK_SAMPLE_COUNT_1_BIT;
memset(gfx_pipeline->stage_indices, ~0, sizeof(gfx_pipeline->stage_indices));
@ -1906,27 +1775,21 @@ pvr_graphics_pipeline_init(struct pvr_device *device,
gfx_pipeline->base.layout =
pvr_pipeline_layout_from_handle(pCreateInfo->layout);
if (ms_info) {
gfx_pipeline->rasterization_samples = ms_info->rasterizationSamples;
gfx_pipeline->sample_mask =
(ms_info->pSampleMask) ? ms_info->pSampleMask[0] : 0xFFFFFFFF;
} else {
gfx_pipeline->rasterization_samples = VK_SAMPLE_COUNT_1_BIT;
gfx_pipeline->sample_mask = 0xFFFFFFFF;
}
/* Compiles and uploads shaders and PDS programs. */
result = pvr_graphics_pipeline_compile(device,
pipeline_cache,
pCreateInfo,
allocator,
gfx_pipeline);
if (result != VK_SUCCESS) {
pvr_pipeline_finish(&gfx_pipeline->base);
return result;
}
if (result != VK_SUCCESS)
goto err_pipeline_finish;
return VK_SUCCESS;
err_pipeline_finish:
pvr_pipeline_finish(&gfx_pipeline->base);
return result;
}
/* If allocator == NULL, the internal one will be used. */

138
src/imagination/vulkan/pvr_private.h
View file

@ -56,6 +56,7 @@
#include "vk_buffer.h"
#include "vk_command_buffer.h"
#include "vk_device.h"
#include "vk_graphics_state.h"
#include "vk_image.h"
#include "vk_instance.h"
#include "vk_log.h"
@ -880,63 +881,6 @@ struct pvr_deferred_cs_command {
};
};
#define PVR_DYNAMIC_STATE_BIT_VIEWPORT BITFIELD_BIT(0U)
#define PVR_DYNAMIC_STATE_BIT_SCISSOR BITFIELD_BIT(1U)
#define PVR_DYNAMIC_STATE_BIT_LINE_WIDTH BITFIELD_BIT(2U)
#define PVR_DYNAMIC_STATE_BIT_DEPTH_BIAS BITFIELD_BIT(3U)
#define PVR_DYNAMIC_STATE_BIT_STENCIL_COMPARE_MASK BITFIELD_BIT(4U)
#define PVR_DYNAMIC_STATE_BIT_STENCIL_WRITE_MASK BITFIELD_BIT(5U)
#define PVR_DYNAMIC_STATE_BIT_STENCIL_REFERENCE BITFIELD_BIT(6U)
#define PVR_DYNAMIC_STATE_BIT_BLEND_CONSTANTS BITFIELD_BIT(7U)
#define PVR_DYNAMIC_STATE_ALL_BITS \
((PVR_DYNAMIC_STATE_BIT_BLEND_CONSTANTS << 1U) - 1U)
struct pvr_dynamic_state {
/* Identifies which pipeline state is static or dynamic.
* To test for dynamic: & PVR_STATE_BITS_...
*/
uint32_t mask;
struct {
/* TODO: fixme in the original code - figure out what. */
uint32_t count;
VkViewport viewports[PVR_MAX_VIEWPORTS];
} viewport;
struct {
/* TODO: fixme in the original code - figure out what. */
uint32_t count;
VkRect2D scissors[PVR_MAX_VIEWPORTS];
} scissor;
/* Saved information from pCreateInfo. */
float line_width;
/* Do not change this. This is the format used for the depth_bias_array
* elements uploaded to the device.
*/
struct pvr_depth_bias_state {
/* Saved information from pCreateInfo. */
float constant_factor;
float slope_factor;
float clamp;
} depth_bias;
float blend_constants[4];
struct {
uint32_t front;
uint32_t back;
} compare_mask;
struct {
uint32_t front;
uint32_t back;
} write_mask;
struct {
uint32_t front;
uint32_t back;
} reference;
};
struct pvr_cmd_buffer_draw_state {
uint32_t base_instance;
uint32_t base_vertex;
@ -960,10 +904,6 @@ struct pvr_cmd_buffer_state {
struct PVRX(TA_STATE_HEADER) emit_header;
struct {
struct pvr_dynamic_state common;
} dynamic;
struct pvr_vertex_binding vertex_bindings[PVR_MAX_VERTEX_INPUT_BINDINGS];
struct {
@ -988,9 +928,6 @@ struct pvr_cmd_buffer_state {
VkFormat depth_format;
struct {
bool viewport : 1;
bool scissor : 1;
bool compute_pipeline_binding : 1;
bool compute_desc_dirty : 1;
@ -1002,16 +939,6 @@ struct pvr_cmd_buffer_state {
bool vertex_descriptors : 1;
bool fragment_descriptors : 1;
bool line_width : 1;
bool depth_bias : 1;
bool blend_constants : 1;
bool compare_mask : 1;
bool write_mask : 1;
bool reference : 1;
bool isp_userpass : 1;
/* Some draw state needs to be tracked for changes between draw calls
@ -1040,6 +967,26 @@ struct pvr_cmd_buffer_state {
uint32_t pds_compute_descriptor_data_offset;
};
/* Do not change this. This is the format used for the depth_bias_array
* elements uploaded to the device.
*/
struct pvr_depth_bias_state {
/* Saved information from pCreateInfo. */
float constant_factor;
float slope_factor;
float clamp;
};
/* Do not change this. This is the format used for the scissor_array
* elements uploaded to the device.
*/
struct pvr_scissor_words {
/* Contains a packed IPF_SCISSOR_WORD_0. */
uint32_t w0;
/* Contains a packed IPF_SCISSOR_WORD_1. */
uint32_t w1;
};
struct pvr_cmd_buffer {
struct vk_command_buffer vk;
@ -1048,10 +995,12 @@ struct pvr_cmd_buffer {
/* Buffer usage flags */
VkCommandBufferUsageFlags usage_flags;
/* Array of struct pvr_depth_bias_state. */
struct util_dynarray depth_bias_array;
/* Array of struct pvr_scissor_words. */
struct util_dynarray scissor_array;
uint32_t scissor_words[2];
struct pvr_scissor_words scissor_words;
struct pvr_cmd_buffer_state state;
@ -1248,44 +1197,15 @@ struct pvr_compute_pipeline {
struct pvr_graphics_pipeline {
struct pvr_pipeline base;
VkSampleCountFlagBits rasterization_samples;
struct pvr_raster_state {
/* Derived and other state. */
/* Indicates whether primitives are discarded immediately before the
* rasterization stage.
*/
bool discard_enable;
VkCullModeFlags cull_mode;
VkFrontFace front_face;
bool depth_bias_enable;
bool depth_clamp_enable;
} raster_state;
struct {
VkPrimitiveTopology topology;
bool primitive_restart;
} input_asm_state;
uint32_t sample_mask;
struct pvr_dynamic_state dynamic_state;
VkCompareOp depth_compare_op;
bool depth_write_disable;
struct {
VkCompareOp compare_op;
/* SOP1 */
VkStencilOp fail_op;
/* SOP2 */
VkStencilOp depth_fail_op;
/* SOP3 */
VkStencilOp pass_op;
} stencil_front, stencil_back;
struct vk_dynamic_graphics_state dynamic_state;
/* Derived and other state */
size_t stage_indices[MESA_SHADER_FRAGMENT + 1];
struct pvr_vertex_shader_state vertex_shader_state;
struct pvr_fragment_shader_state fragment_shader_state;
struct {
struct pvr_vertex_shader_state vertex;
struct pvr_fragment_shader_state fragment;
} shader_state;
};
struct pvr_query_pool {