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Merge commit 'origin/tgsi-simplify-ext'

Browse source 
Conflicts:
	src/gallium/drivers/r300/r300_vs.c
This commit is contained in:
Keith Whitwell 2009-12-01 14:31:14 +00:00
commit 87eec80c11
104 changed files with 1718 additions and 2500 deletions
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93
src/gallium/auxiliary/draw/draw_pipe_aaline.c
View file

@ -139,29 +139,29 @@ aa_transform_decl(struct tgsi_transform_context *ctx,
struct aa_transform_context *aactx = (struct aa_transform_context *) ctx;
if (decl->Declaration.File == TGSI_FILE_OUTPUT &&
decl->Semantic.SemanticName == TGSI_SEMANTIC_COLOR &&
decl->Semantic.SemanticIndex == 0) {
aactx->colorOutput = decl->DeclarationRange.First;
decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
decl->Semantic.Index == 0) {
aactx->colorOutput = decl->Range.First;
}
else if (decl->Declaration.File == TGSI_FILE_SAMPLER) {
uint i;
for (i = decl->DeclarationRange.First;
i <= decl->DeclarationRange.Last; i++) {
for (i = decl->Range.First;
i <= decl->Range.Last; i++) {
aactx->samplersUsed |= 1 << i;
}
}
else if (decl->Declaration.File == TGSI_FILE_INPUT) {
if ((int) decl->DeclarationRange.Last > aactx->maxInput)
aactx->maxInput = decl->DeclarationRange.Last;
if (decl->Semantic.SemanticName == TGSI_SEMANTIC_GENERIC &&
(int) decl->Semantic.SemanticIndex > aactx->maxGeneric) {
aactx->maxGeneric = decl->Semantic.SemanticIndex;
if ((int) decl->Range.Last > aactx->maxInput)
aactx->maxInput = decl->Range.Last;
if (decl->Semantic.Name == TGSI_SEMANTIC_GENERIC &&
(int) decl->Semantic.Index > aactx->maxGeneric) {
aactx->maxGeneric = decl->Semantic.Index;
}
}
else if (decl->Declaration.File == TGSI_FILE_TEMPORARY) {
uint i;
for (i = decl->DeclarationRange.First;
i <= decl->DeclarationRange.Last; i++) {
for (i = decl->Range.First;
i <= decl->Range.Last; i++) {
aactx->tempsUsed |= (1 << i);
}
}
@ -228,30 +228,30 @@ aa_transform_inst(struct tgsi_transform_context *ctx,
/* XXX this could be linear... */
decl.Declaration.Interpolate = TGSI_INTERPOLATE_PERSPECTIVE;
decl.Declaration.Semantic = 1;
decl.Semantic.SemanticName = TGSI_SEMANTIC_GENERIC;
decl.Semantic.SemanticIndex = aactx->maxGeneric + 1;
decl.DeclarationRange.First =
decl.DeclarationRange.Last = aactx->maxInput + 1;
decl.Semantic.Name = TGSI_SEMANTIC_GENERIC;
decl.Semantic.Index = aactx->maxGeneric + 1;
decl.Range.First =
decl.Range.Last = aactx->maxInput + 1;
ctx->emit_declaration(ctx, &decl);
/* declare new sampler */
decl = tgsi_default_full_declaration();
decl.Declaration.File = TGSI_FILE_SAMPLER;
decl.DeclarationRange.First =
decl.DeclarationRange.Last = aactx->freeSampler;
decl.Range.First =
decl.Range.Last = aactx->freeSampler;
ctx->emit_declaration(ctx, &decl);
/* declare new temp regs */
decl = tgsi_default_full_declaration();
decl.Declaration.File = TGSI_FILE_TEMPORARY;
decl.DeclarationRange.First =
decl.DeclarationRange.Last = aactx->texTemp;
decl.Range.First =
decl.Range.Last = aactx->texTemp;
ctx->emit_declaration(ctx, &decl);
decl = tgsi_default_full_declaration();
decl.Declaration.File = TGSI_FILE_TEMPORARY;
decl.DeclarationRange.First =
decl.DeclarationRange.Last = aactx->colorTemp;
decl.Range.First =
decl.Range.Last = aactx->colorTemp;
ctx->emit_declaration(ctx, &decl);
aactx->firstInstruction = FALSE;
@ -265,14 +265,15 @@ aa_transform_inst(struct tgsi_transform_context *ctx,
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_TEX;
newInst.Instruction.NumDstRegs = 1;
newInst.FullDstRegisters[0].DstRegister.File = TGSI_FILE_TEMPORARY;
newInst.FullDstRegisters[0].DstRegister.Index = aactx->texTemp;
newInst.Dst[0].Register.File = TGSI_FILE_TEMPORARY;
newInst.Dst[0].Register.Index = aactx->texTemp;
newInst.Instruction.NumSrcRegs = 2;
newInst.InstructionExtTexture.Texture = TGSI_TEXTURE_2D;
newInst.FullSrcRegisters[0].SrcRegister.File = TGSI_FILE_INPUT;
newInst.FullSrcRegisters[0].SrcRegister.Index = aactx->maxInput + 1;
newInst.FullSrcRegisters[1].SrcRegister.File = TGSI_FILE_SAMPLER;
newInst.FullSrcRegisters[1].SrcRegister.Index = aactx->freeSampler;
newInst.Instruction.Texture = TRUE;
newInst.Texture.Texture = TGSI_TEXTURE_2D;
newInst.Src[0].Register.File = TGSI_FILE_INPUT;
newInst.Src[0].Register.Index = aactx->maxInput + 1;
newInst.Src[1].Register.File = TGSI_FILE_SAMPLER;
newInst.Src[1].Register.Index = aactx->freeSampler;
ctx->emit_instruction(ctx, &newInst);
@ -280,26 +281,26 @@ aa_transform_inst(struct tgsi_transform_context *ctx,
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_MOV;
newInst.Instruction.NumDstRegs = 1;
newInst.FullDstRegisters[0].DstRegister.File = TGSI_FILE_OUTPUT;
newInst.FullDstRegisters[0].DstRegister.Index = aactx->colorOutput;
newInst.FullDstRegisters[0].DstRegister.WriteMask = TGSI_WRITEMASK_XYZ;
newInst.Dst[0].Register.File = TGSI_FILE_OUTPUT;
newInst.Dst[0].Register.Index = aactx->colorOutput;
newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_XYZ;
newInst.Instruction.NumSrcRegs = 1;
newInst.FullSrcRegisters[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
newInst.FullSrcRegisters[0].SrcRegister.Index = aactx->colorTemp;
newInst.Src[0].Register.File = TGSI_FILE_TEMPORARY;
newInst.Src[0].Register.Index = aactx->colorTemp;
ctx->emit_instruction(ctx, &newInst);
/* MUL alpha */
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_MUL;
newInst.Instruction.NumDstRegs = 1;
newInst.FullDstRegisters[0].DstRegister.File = TGSI_FILE_OUTPUT;
newInst.FullDstRegisters[0].DstRegister.Index = aactx->colorOutput;
newInst.FullDstRegisters[0].DstRegister.WriteMask = TGSI_WRITEMASK_W;
newInst.Dst[0].Register.File = TGSI_FILE_OUTPUT;
newInst.Dst[0].Register.Index = aactx->colorOutput;
newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_W;
newInst.Instruction.NumSrcRegs = 2;
newInst.FullSrcRegisters[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
newInst.FullSrcRegisters[0].SrcRegister.Index = aactx->colorTemp;
newInst.FullSrcRegisters[1].SrcRegister.File = TGSI_FILE_TEMPORARY;
newInst.FullSrcRegisters[1].SrcRegister.Index = aactx->texTemp;
newInst.Src[0].Register.File = TGSI_FILE_TEMPORARY;
newInst.Src[0].Register.Index = aactx->colorTemp;
newInst.Src[1].Register.File = TGSI_FILE_TEMPORARY;
newInst.Src[1].Register.Index = aactx->texTemp;
ctx->emit_instruction(ctx, &newInst);
/* END */
@ -316,11 +317,11 @@ aa_transform_inst(struct tgsi_transform_context *ctx,
uint i;
for (i = 0; i < inst->Instruction.NumDstRegs; i++) {
struct tgsi_full_dst_register *dst = &inst->FullDstRegisters[i];
if (dst->DstRegister.File == TGSI_FILE_OUTPUT &&
dst->DstRegister.Index == aactx->colorOutput) {
dst->DstRegister.File = TGSI_FILE_TEMPORARY;
dst->DstRegister.Index = aactx->colorTemp;
struct tgsi_full_dst_register *dst = &inst->Dst[i];
if (dst->Register.File == TGSI_FILE_OUTPUT &&
dst->Register.Index == aactx->colorOutput) {
dst->Register.File = TGSI_FILE_TEMPORARY;
dst->Register.Index = aactx->colorTemp;
}
}

282
src/gallium/auxiliary/draw/draw_pipe_aapoint.c
View file

@ -131,22 +131,22 @@ aa_transform_decl(struct tgsi_transform_context *ctx,
struct aa_transform_context *aactx = (struct aa_transform_context *) ctx;
if (decl->Declaration.File == TGSI_FILE_OUTPUT &&
decl->Semantic.SemanticName == TGSI_SEMANTIC_COLOR &&
decl->Semantic.SemanticIndex == 0) {
aactx->colorOutput = decl->DeclarationRange.First;
decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
decl->Semantic.Index == 0) {
aactx->colorOutput = decl->Range.First;
}
else if (decl->Declaration.File == TGSI_FILE_INPUT) {
if ((int) decl->DeclarationRange.Last > aactx->maxInput)
aactx->maxInput = decl->DeclarationRange.Last;
if (decl->Semantic.SemanticName == TGSI_SEMANTIC_GENERIC &&
(int) decl->Semantic.SemanticIndex > aactx->maxGeneric) {
aactx->maxGeneric = decl->Semantic.SemanticIndex;
if ((int) decl->Range.Last > aactx->maxInput)
aactx->maxInput = decl->Range.Last;
if (decl->Semantic.Name == TGSI_SEMANTIC_GENERIC &&
(int) decl->Semantic.Index > aactx->maxGeneric) {
aactx->maxGeneric = decl->Semantic.Index;
}
}
else if (decl->Declaration.File == TGSI_FILE_TEMPORARY) {
uint i;
for (i = decl->DeclarationRange.First;
i <= decl->DeclarationRange.Last; i++) {
for (i = decl->Range.First;
i <= decl->Range.Last; i++) {
aactx->tempsUsed |= (1 << i);
}
}
@ -198,23 +198,23 @@ aa_transform_inst(struct tgsi_transform_context *ctx,
/* XXX this could be linear... */
decl.Declaration.Interpolate = TGSI_INTERPOLATE_PERSPECTIVE;
decl.Declaration.Semantic = 1;
decl.Semantic.SemanticName = TGSI_SEMANTIC_GENERIC;
decl.Semantic.SemanticIndex = aactx->maxGeneric + 1;
decl.DeclarationRange.First =
decl.DeclarationRange.Last = texInput;
decl.Semantic.Name = TGSI_SEMANTIC_GENERIC;
decl.Semantic.Index = aactx->maxGeneric + 1;
decl.Range.First =
decl.Range.Last = texInput;
ctx->emit_declaration(ctx, &decl);
/* declare new temp regs */
decl = tgsi_default_full_declaration();
decl.Declaration.File = TGSI_FILE_TEMPORARY;
decl.DeclarationRange.First =
decl.DeclarationRange.Last = tmp0;
decl.Range.First =
decl.Range.Last = tmp0;
ctx->emit_declaration(ctx, &decl);
decl = tgsi_default_full_declaration();
decl.Declaration.File = TGSI_FILE_TEMPORARY;
decl.DeclarationRange.First =
decl.DeclarationRange.Last = aactx->colorTemp;
decl.Range.First =
decl.Range.Last = aactx->colorTemp;
ctx->emit_declaration(ctx, &decl);
aactx->firstInstruction = FALSE;
@ -234,30 +234,30 @@ aa_transform_inst(struct tgsi_transform_context *ctx,
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_MUL;
newInst.Instruction.NumDstRegs = 1;
newInst.FullDstRegisters[0].DstRegister.File = TGSI_FILE_TEMPORARY;
newInst.FullDstRegisters[0].DstRegister.Index = tmp0;
newInst.FullDstRegisters[0].DstRegister.WriteMask = TGSI_WRITEMASK_XY;
newInst.Dst[0].Register.File = TGSI_FILE_TEMPORARY;
newInst.Dst[0].Register.Index = tmp0;
newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_XY;
newInst.Instruction.NumSrcRegs = 2;
newInst.FullSrcRegisters[0].SrcRegister.File = TGSI_FILE_INPUT;
newInst.FullSrcRegisters[0].SrcRegister.Index = texInput;
newInst.FullSrcRegisters[1].SrcRegister.File = TGSI_FILE_INPUT;
newInst.FullSrcRegisters[1].SrcRegister.Index = texInput;
newInst.Src[0].Register.File = TGSI_FILE_INPUT;
newInst.Src[0].Register.Index = texInput;
newInst.Src[1].Register.File = TGSI_FILE_INPUT;
newInst.Src[1].Register.Index = texInput;
ctx->emit_instruction(ctx, &newInst);
/* ADD t0.x, t0.x, t0.y; # x^2 + y^2 */
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_ADD;
newInst.Instruction.NumDstRegs = 1;
newInst.FullDstRegisters[0].DstRegister.File = TGSI_FILE_TEMPORARY;
newInst.FullDstRegisters[0].DstRegister.Index = tmp0;
newInst.FullDstRegisters[0].DstRegister.WriteMask = TGSI_WRITEMASK_X;
newInst.Dst[0].Register.File = TGSI_FILE_TEMPORARY;
newInst.Dst[0].Register.Index = tmp0;
newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_X;
newInst.Instruction.NumSrcRegs = 2;
newInst.FullSrcRegisters[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
newInst.FullSrcRegisters[0].SrcRegister.Index = tmp0;
newInst.FullSrcRegisters[0].SrcRegister.SwizzleX = TGSI_SWIZZLE_X;
newInst.FullSrcRegisters[1].SrcRegister.File = TGSI_FILE_TEMPORARY;
newInst.FullSrcRegisters[1].SrcRegister.Index = tmp0;
newInst.FullSrcRegisters[1].SrcRegister.SwizzleX = TGSI_SWIZZLE_Y;
newInst.Src[0].Register.File = TGSI_FILE_TEMPORARY;
newInst.Src[0].Register.Index = tmp0;
newInst.Src[0].Register.SwizzleX = TGSI_SWIZZLE_X;
newInst.Src[1].Register.File = TGSI_FILE_TEMPORARY;
newInst.Src[1].Register.Index = tmp0;
newInst.Src[1].Register.SwizzleX = TGSI_SWIZZLE_Y;
ctx->emit_instruction(ctx, &newInst);
#if NORMALIZE /* OPTIONAL normalization of length */
@ -265,24 +265,24 @@ aa_transform_inst(struct tgsi_transform_context *ctx,
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_RSQ;
newInst.Instruction.NumDstRegs = 1;
newInst.FullDstRegisters[0].DstRegister.File = TGSI_FILE_TEMPORARY;
newInst.FullDstRegisters[0].DstRegister.Index = tmp0;
newInst.FullDstRegisters[0].DstRegister.WriteMask = TGSI_WRITEMASK_X;
newInst.Dst[0].Register.File = TGSI_FILE_TEMPORARY;
newInst.Dst[0].Register.Index = tmp0;
newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_X;
newInst.Instruction.NumSrcRegs = 1;
newInst.FullSrcRegisters[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
newInst.FullSrcRegisters[0].SrcRegister.Index = tmp0;
newInst.Src[0].Register.File = TGSI_FILE_TEMPORARY;
newInst.Src[0].Register.Index = tmp0;
ctx->emit_instruction(ctx, &newInst);
/* RCP t0.x, t0.x; */
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_RCP;
newInst.Instruction.NumDstRegs = 1;
newInst.FullDstRegisters[0].DstRegister.File = TGSI_FILE_TEMPORARY;
newInst.FullDstRegisters[0].DstRegister.Index = tmp0;
newInst.FullDstRegisters[0].DstRegister.WriteMask = TGSI_WRITEMASK_X;
newInst.Dst[0].Register.File = TGSI_FILE_TEMPORARY;
newInst.Dst[0].Register.Index = tmp0;
newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_X;
newInst.Instruction.NumSrcRegs = 1;
newInst.FullSrcRegisters[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
newInst.FullSrcRegisters[0].SrcRegister.Index = tmp0;
newInst.Src[0].Register.File = TGSI_FILE_TEMPORARY;
newInst.Src[0].Register.Index = tmp0;
ctx->emit_instruction(ctx, &newInst);
#endif
@ -290,16 +290,16 @@ aa_transform_inst(struct tgsi_transform_context *ctx,
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_SGT;
newInst.Instruction.NumDstRegs = 1;
newInst.FullDstRegisters[0].DstRegister.File = TGSI_FILE_TEMPORARY;
newInst.FullDstRegisters[0].DstRegister.Index = tmp0;
newInst.FullDstRegisters[0].DstRegister.WriteMask = TGSI_WRITEMASK_Y;
newInst.Dst[0].Register.File = TGSI_FILE_TEMPORARY;
newInst.Dst[0].Register.Index = tmp0;
newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_Y;
newInst.Instruction.NumSrcRegs = 2;
newInst.FullSrcRegisters[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
newInst.FullSrcRegisters[0].SrcRegister.Index = tmp0;
newInst.FullSrcRegisters[0].SrcRegister.SwizzleY = TGSI_SWIZZLE_X;
newInst.FullSrcRegisters[1].SrcRegister.File = TGSI_FILE_INPUT;
newInst.FullSrcRegisters[1].SrcRegister.Index = texInput;
newInst.FullSrcRegisters[1].SrcRegister.SwizzleY = TGSI_SWIZZLE_W;
newInst.Src[0].Register.File = TGSI_FILE_TEMPORARY;
newInst.Src[0].Register.Index = tmp0;
newInst.Src[0].Register.SwizzleY = TGSI_SWIZZLE_X;
newInst.Src[1].Register.File = TGSI_FILE_INPUT;
newInst.Src[1].Register.Index = texInput;
newInst.Src[1].Register.SwizzleY = TGSI_SWIZZLE_W;
ctx->emit_instruction(ctx, &newInst);
/* KIL -tmp0.yyyy; # if -tmp0.y < 0, KILL */
@ -307,13 +307,13 @@ aa_transform_inst(struct tgsi_transform_context *ctx,
newInst.Instruction.Opcode = TGSI_OPCODE_KIL;
newInst.Instruction.NumDstRegs = 0;
newInst.Instruction.NumSrcRegs = 1;
newInst.FullSrcRegisters[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
newInst.FullSrcRegisters[0].SrcRegister.Index = tmp0;
newInst.FullSrcRegisters[0].SrcRegister.SwizzleX = TGSI_SWIZZLE_Y;
newInst.FullSrcRegisters[0].SrcRegister.SwizzleY = TGSI_SWIZZLE_Y;
newInst.FullSrcRegisters[0].SrcRegister.SwizzleZ = TGSI_SWIZZLE_Y;
newInst.FullSrcRegisters[0].SrcRegister.SwizzleW = TGSI_SWIZZLE_Y;
newInst.FullSrcRegisters[0].SrcRegister.Negate = 1;
newInst.Src[0].Register.File = TGSI_FILE_TEMPORARY;
newInst.Src[0].Register.Index = tmp0;
newInst.Src[0].Register.SwizzleX = TGSI_SWIZZLE_Y;
newInst.Src[0].Register.SwizzleY = TGSI_SWIZZLE_Y;
newInst.Src[0].Register.SwizzleZ = TGSI_SWIZZLE_Y;
newInst.Src[0].Register.SwizzleW = TGSI_SWIZZLE_Y;
newInst.Src[0].Register.Negate = 1;
ctx->emit_instruction(ctx, &newInst);
@ -323,77 +323,77 @@ aa_transform_inst(struct tgsi_transform_context *ctx,
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_SUB;
newInst.Instruction.NumDstRegs = 1;
newInst.FullDstRegisters[0].DstRegister.File = TGSI_FILE_TEMPORARY;
newInst.FullDstRegisters[0].DstRegister.Index = tmp0;
newInst.FullDstRegisters[0].DstRegister.WriteMask = TGSI_WRITEMASK_Z;
newInst.Dst[0].Register.File = TGSI_FILE_TEMPORARY;
newInst.Dst[0].Register.Index = tmp0;
newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_Z;
newInst.Instruction.NumSrcRegs = 2;
newInst.FullSrcRegisters[0].SrcRegister.File = TGSI_FILE_INPUT;
newInst.FullSrcRegisters[0].SrcRegister.Index = texInput;
newInst.FullSrcRegisters[0].SrcRegister.SwizzleZ = TGSI_SWIZZLE_W;
newInst.FullSrcRegisters[1].SrcRegister.File = TGSI_FILE_INPUT;
newInst.FullSrcRegisters[1].SrcRegister.Index = texInput;
newInst.FullSrcRegisters[1].SrcRegister.SwizzleZ = TGSI_SWIZZLE_Z;
newInst.Src[0].Register.File = TGSI_FILE_INPUT;
newInst.Src[0].Register.Index = texInput;
newInst.Src[0].Register.SwizzleZ = TGSI_SWIZZLE_W;
newInst.Src[1].Register.File = TGSI_FILE_INPUT;
newInst.Src[1].Register.Index = texInput;
newInst.Src[1].Register.SwizzleZ = TGSI_SWIZZLE_Z;
ctx->emit_instruction(ctx, &newInst);
/* RCP t0.z, t0.z; # t0.z = 1 / m */
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_RCP;
newInst.Instruction.NumDstRegs = 1;
newInst.FullDstRegisters[0].DstRegister.File = TGSI_FILE_TEMPORARY;
newInst.FullDstRegisters[0].DstRegister.Index = tmp0;
newInst.FullDstRegisters[0].DstRegister.WriteMask = TGSI_WRITEMASK_Z;
newInst.Dst[0].Register.File = TGSI_FILE_TEMPORARY;
newInst.Dst[0].Register.Index = tmp0;
newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_Z;
newInst.Instruction.NumSrcRegs = 1;
newInst.FullSrcRegisters[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
newInst.FullSrcRegisters[0].SrcRegister.Index = tmp0;
newInst.FullSrcRegisters[0].SrcRegister.SwizzleX = TGSI_SWIZZLE_Z;
newInst.Src[0].Register.File = TGSI_FILE_TEMPORARY;
newInst.Src[0].Register.Index = tmp0;
newInst.Src[0].Register.SwizzleX = TGSI_SWIZZLE_Z;
ctx->emit_instruction(ctx, &newInst);
/* SUB t0.y, 1, t0.x; # d = 1 - d */
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_SUB;
newInst.Instruction.NumDstRegs = 1;
newInst.FullDstRegisters[0].DstRegister.File = TGSI_FILE_TEMPORARY;
newInst.FullDstRegisters[0].DstRegister.Index = tmp0;
newInst.FullDstRegisters[0].DstRegister.WriteMask = TGSI_WRITEMASK_Y;
newInst.Dst[0].Register.File = TGSI_FILE_TEMPORARY;
newInst.Dst[0].Register.Index = tmp0;
newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_Y;
newInst.Instruction.NumSrcRegs = 2;
newInst.FullSrcRegisters[0].SrcRegister.File = TGSI_FILE_INPUT;
newInst.FullSrcRegisters[0].SrcRegister.Index = texInput;
newInst.FullSrcRegisters[0].SrcRegister.SwizzleY = TGSI_SWIZZLE_W;
newInst.FullSrcRegisters[1].SrcRegister.File = TGSI_FILE_TEMPORARY;
newInst.FullSrcRegisters[1].SrcRegister.Index = tmp0;
newInst.FullSrcRegisters[1].SrcRegister.SwizzleY = TGSI_SWIZZLE_X;
newInst.Src[0].Register.File = TGSI_FILE_INPUT;
newInst.Src[0].Register.Index = texInput;
newInst.Src[0].Register.SwizzleY = TGSI_SWIZZLE_W;
newInst.Src[1].Register.File = TGSI_FILE_TEMPORARY;
newInst.Src[1].Register.Index = tmp0;
newInst.Src[1].Register.SwizzleY = TGSI_SWIZZLE_X;
ctx->emit_instruction(ctx, &newInst);
/* MUL t0.w, t0.y, t0.z; # coverage = d * m */
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_MUL;
newInst.Instruction.NumDstRegs = 1;
newInst.FullDstRegisters[0].DstRegister.File = TGSI_FILE_TEMPORARY;
newInst.FullDstRegisters[0].DstRegister.Index = tmp0;
newInst.FullDstRegisters[0].DstRegister.WriteMask = TGSI_WRITEMASK_W;
newInst.Dst[0].Register.File = TGSI_FILE_TEMPORARY;
newInst.Dst[0].Register.Index = tmp0;
newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_W;
newInst.Instruction.NumSrcRegs = 2;
newInst.FullSrcRegisters[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
newInst.FullSrcRegisters[0].SrcRegister.Index = tmp0;
newInst.FullSrcRegisters[0].SrcRegister.SwizzleW = TGSI_SWIZZLE_Y;
newInst.FullSrcRegisters[1].SrcRegister.File = TGSI_FILE_TEMPORARY;
newInst.FullSrcRegisters[1].SrcRegister.Index = tmp0;
newInst.FullSrcRegisters[1].SrcRegister.SwizzleW = TGSI_SWIZZLE_Z;
newInst.Src[0].Register.File = TGSI_FILE_TEMPORARY;
newInst.Src[0].Register.Index = tmp0;
newInst.Src[0].Register.SwizzleW = TGSI_SWIZZLE_Y;
newInst.Src[1].Register.File = TGSI_FILE_TEMPORARY;
newInst.Src[1].Register.Index = tmp0;
newInst.Src[1].Register.SwizzleW = TGSI_SWIZZLE_Z;
ctx->emit_instruction(ctx, &newInst);
/* SLE t0.y, t0.x, tex.z; # bool b = distance <= k */
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_SLE;
newInst.Instruction.NumDstRegs = 1;
newInst.FullDstRegisters[0].DstRegister.File = TGSI_FILE_TEMPORARY;
newInst.FullDstRegisters[0].DstRegister.Index = tmp0;
newInst.FullDstRegisters[0].DstRegister.WriteMask = TGSI_WRITEMASK_Y;
newInst.Dst[0].Register.File = TGSI_FILE_TEMPORARY;
newInst.Dst[0].Register.Index = tmp0;
newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_Y;
newInst.Instruction.NumSrcRegs = 2;
newInst.FullSrcRegisters[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
newInst.FullSrcRegisters[0].SrcRegister.Index = tmp0;
newInst.FullSrcRegisters[0].SrcRegister.SwizzleY = TGSI_SWIZZLE_X;
newInst.FullSrcRegisters[1].SrcRegister.File = TGSI_FILE_INPUT;
newInst.FullSrcRegisters[1].SrcRegister.Index = texInput;
newInst.FullSrcRegisters[1].SrcRegister.SwizzleY = TGSI_SWIZZLE_Z;
newInst.Src[0].Register.File = TGSI_FILE_TEMPORARY;
newInst.Src[0].Register.Index = tmp0;
newInst.Src[0].Register.SwizzleY = TGSI_SWIZZLE_X;
newInst.Src[1].Register.File = TGSI_FILE_INPUT;
newInst.Src[1].Register.Index = texInput;
newInst.Src[1].Register.SwizzleY = TGSI_SWIZZLE_Z;
ctx->emit_instruction(ctx, &newInst);
/* CMP t0.w, -t0.y, tex.w, t0.w;
@ -405,29 +405,29 @@ aa_transform_inst(struct tgsi_transform_context *ctx,
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_CMP;
newInst.Instruction.NumDstRegs = 1;
newInst.FullDstRegisters[0].DstRegister.File = TGSI_FILE_TEMPORARY;
newInst.FullDstRegisters[0].DstRegister.Index = tmp0;
newInst.FullDstRegisters[0].DstRegister.WriteMask = TGSI_WRITEMASK_W;
newInst.Dst[0].Register.File = TGSI_FILE_TEMPORARY;
newInst.Dst[0].Register.Index = tmp0;
newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_W;
newInst.Instruction.NumSrcRegs = 3;
newInst.FullSrcRegisters[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
newInst.FullSrcRegisters[0].SrcRegister.Index = tmp0;
newInst.FullSrcRegisters[0].SrcRegister.SwizzleX = TGSI_SWIZZLE_Y;
newInst.FullSrcRegisters[0].SrcRegister.SwizzleY = TGSI_SWIZZLE_Y;
newInst.FullSrcRegisters[0].SrcRegister.SwizzleZ = TGSI_SWIZZLE_Y;
newInst.FullSrcRegisters[0].SrcRegister.SwizzleW = TGSI_SWIZZLE_Y;
newInst.FullSrcRegisters[0].SrcRegister.Negate = 1;
newInst.FullSrcRegisters[1].SrcRegister.File = TGSI_FILE_INPUT;
newInst.FullSrcRegisters[1].SrcRegister.Index = texInput;
newInst.FullSrcRegisters[1].SrcRegister.SwizzleX = TGSI_SWIZZLE_W;
newInst.FullSrcRegisters[1].SrcRegister.SwizzleY = TGSI_SWIZZLE_W;
newInst.FullSrcRegisters[1].SrcRegister.SwizzleZ = TGSI_SWIZZLE_W;
newInst.FullSrcRegisters[1].SrcRegister.SwizzleW = TGSI_SWIZZLE_W;
newInst.FullSrcRegisters[2].SrcRegister.File = TGSI_FILE_TEMPORARY;
newInst.FullSrcRegisters[2].SrcRegister.Index = tmp0;
newInst.FullSrcRegisters[2].SrcRegister.SwizzleX = TGSI_SWIZZLE_W;
newInst.FullSrcRegisters[2].SrcRegister.SwizzleY = TGSI_SWIZZLE_W;
newInst.FullSrcRegisters[2].SrcRegister.SwizzleZ = TGSI_SWIZZLE_W;
newInst.FullSrcRegisters[2].SrcRegister.SwizzleW = TGSI_SWIZZLE_W;
newInst.Src[0].Register.File = TGSI_FILE_TEMPORARY;
newInst.Src[0].Register.Index = tmp0;
newInst.Src[0].Register.SwizzleX = TGSI_SWIZZLE_Y;
newInst.Src[0].Register.SwizzleY = TGSI_SWIZZLE_Y;
newInst.Src[0].Register.SwizzleZ = TGSI_SWIZZLE_Y;
newInst.Src[0].Register.SwizzleW = TGSI_SWIZZLE_Y;
newInst.Src[0].Register.Negate = 1;
newInst.Src[1].Register.File = TGSI_FILE_INPUT;
newInst.Src[1].Register.Index = texInput;
newInst.Src[1].Register.SwizzleX = TGSI_SWIZZLE_W;
newInst.Src[1].Register.SwizzleY = TGSI_SWIZZLE_W;
newInst.Src[1].Register.SwizzleZ = TGSI_SWIZZLE_W;
newInst.Src[1].Register.SwizzleW = TGSI_SWIZZLE_W;
newInst.Src[2].Register.File = TGSI_FILE_TEMPORARY;
newInst.Src[2].Register.Index = tmp0;
newInst.Src[2].Register.SwizzleX = TGSI_SWIZZLE_W;
newInst.Src[2].Register.SwizzleY = TGSI_SWIZZLE_W;
newInst.Src[2].Register.SwizzleZ = TGSI_SWIZZLE_W;
newInst.Src[2].Register.SwizzleW = TGSI_SWIZZLE_W;
ctx->emit_instruction(ctx, &newInst);
}
@ -439,26 +439,26 @@ aa_transform_inst(struct tgsi_transform_context *ctx,
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_MOV;
newInst.Instruction.NumDstRegs = 1;
newInst.FullDstRegisters[0].DstRegister.File = TGSI_FILE_OUTPUT;
newInst.FullDstRegisters[0].DstRegister.Index = aactx->colorOutput;
newInst.FullDstRegisters[0].DstRegister.WriteMask = TGSI_WRITEMASK_XYZ;
newInst.Dst[0].Register.File = TGSI_FILE_OUTPUT;
newInst.Dst[0].Register.Index = aactx->colorOutput;
newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_XYZ;
newInst.Instruction.NumSrcRegs = 1;
newInst.FullSrcRegisters[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
newInst.FullSrcRegisters[0].SrcRegister.Index = aactx->colorTemp;
newInst.Src[0].Register.File = TGSI_FILE_TEMPORARY;
newInst.Src[0].Register.Index = aactx->colorTemp;
ctx->emit_instruction(ctx, &newInst);
/* MUL result.color.w, colorTemp, tmp0.w; */
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_MUL;
newInst.Instruction.NumDstRegs = 1;
newInst.FullDstRegisters[0].DstRegister.File = TGSI_FILE_OUTPUT;
newInst.FullDstRegisters[0].DstRegister.Index = aactx->colorOutput;
newInst.FullDstRegisters[0].DstRegister.WriteMask = TGSI_WRITEMASK_W;
newInst.Dst[0].Register.File = TGSI_FILE_OUTPUT;
newInst.Dst[0].Register.Index = aactx->colorOutput;
newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_W;
newInst.Instruction.NumSrcRegs = 2;
newInst.FullSrcRegisters[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
newInst.FullSrcRegisters[0].SrcRegister.Index = aactx->colorTemp;
newInst.FullSrcRegisters[1].SrcRegister.File = TGSI_FILE_TEMPORARY;
newInst.FullSrcRegisters[1].SrcRegister.Index = aactx->tmp0;
newInst.Src[0].Register.File = TGSI_FILE_TEMPORARY;
newInst.Src[0].Register.Index = aactx->colorTemp;
newInst.Src[1].Register.File = TGSI_FILE_TEMPORARY;
newInst.Src[1].Register.Index = aactx->tmp0;
ctx->emit_instruction(ctx, &newInst);
}
else {
@ -468,11 +468,11 @@ aa_transform_inst(struct tgsi_transform_context *ctx,
uint i;
for (i = 0; i < inst->Instruction.NumDstRegs; i++) {
struct tgsi_full_dst_register *dst = &inst->FullDstRegisters[i];
if (dst->DstRegister.File == TGSI_FILE_OUTPUT &&
dst->DstRegister.Index == aactx->colorOutput) {
dst->DstRegister.File = TGSI_FILE_TEMPORARY;
dst->DstRegister.Index = aactx->colorTemp;
struct tgsi_full_dst_register *dst = &inst->Dst[i];
if (dst->Register.File == TGSI_FILE_OUTPUT &&
dst->Register.Index == aactx->colorOutput) {
dst->Register.File = TGSI_FILE_TEMPORARY;
dst->Register.Index = aactx->colorTemp;
}
}
}

63
src/gallium/auxiliary/draw/draw_pipe_pstipple.c
View file

@ -133,20 +133,20 @@ pstip_transform_decl(struct tgsi_transform_context *ctx,
if (decl->Declaration.File == TGSI_FILE_SAMPLER) {
uint i;
for (i = decl->DeclarationRange.First;
i <= decl->DeclarationRange.Last; i++) {
for (i = decl->Range.First;
i <= decl->Range.Last; i++) {
pctx->samplersUsed |= 1 << i;
}
}
else if (decl->Declaration.File == TGSI_FILE_INPUT) {
pctx->maxInput = MAX2(pctx->maxInput, (int) decl->DeclarationRange.Last);
if (decl->Semantic.SemanticName == TGSI_SEMANTIC_POSITION)
pctx->wincoordInput = (int) decl->DeclarationRange.First;
pctx->maxInput = MAX2(pctx->maxInput, (int) decl->Range.Last);
if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION)
pctx->wincoordInput = (int) decl->Range.First;
}
else if (decl->Declaration.File == TGSI_FILE_TEMPORARY) {
uint i;
for (i = decl->DeclarationRange.First;
i <= decl->DeclarationRange.Last; i++) {
for (i = decl->Range.First;
i <= decl->Range.Last; i++) {
pctx->tempsUsed |= (1 << i);
}
}
@ -226,25 +226,25 @@ pstip_transform_inst(struct tgsi_transform_context *ctx,
decl.Declaration.File = TGSI_FILE_INPUT;
decl.Declaration.Interpolate = TGSI_INTERPOLATE_LINEAR; /* XXX? */
decl.Declaration.Semantic = 1;
decl.Semantic.SemanticName = TGSI_SEMANTIC_POSITION;
decl.Semantic.SemanticIndex = 0;
decl.DeclarationRange.First =
decl.DeclarationRange.Last = wincoordInput;
decl.Semantic.Name = TGSI_SEMANTIC_POSITION;
decl.Semantic.Index = 0;
decl.Range.First =
decl.Range.Last = wincoordInput;
ctx->emit_declaration(ctx, &decl);
}
/* declare new sampler */
decl = tgsi_default_full_declaration();
decl.Declaration.File = TGSI_FILE_SAMPLER;
decl.DeclarationRange.First =
decl.DeclarationRange.Last = pctx->freeSampler;
decl.Range.First =
decl.Range.Last = pctx->freeSampler;
ctx->emit_declaration(ctx, &decl);
/* declare new temp regs */
decl = tgsi_default_full_declaration();
decl.Declaration.File = TGSI_FILE_TEMPORARY;
decl.DeclarationRange.First =
decl.DeclarationRange.Last = pctx->texTemp;
decl.Range.First =
decl.Range.Last = pctx->texTemp;
ctx->emit_declaration(ctx, &decl);
/* emit immediate = {1/32, 1/32, 1, 1}
@ -280,27 +280,28 @@ pstip_transform_inst(struct tgsi_transform_context *ctx,
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_MUL;
newInst.Instruction.NumDstRegs = 1;
newInst.FullDstRegisters[0].DstRegister.File = TGSI_FILE_TEMPORARY;
newInst.FullDstRegisters[0].DstRegister.Index = pctx->texTemp;
newInst.Dst[0].Register.File = TGSI_FILE_TEMPORARY;
newInst.Dst[0].Register.Index = pctx->texTemp;
newInst.Instruction.NumSrcRegs = 2;
newInst.FullSrcRegisters[0].SrcRegister.File = TGSI_FILE_INPUT;
newInst.FullSrcRegisters[0].SrcRegister.Index = wincoordInput;
newInst.FullSrcRegisters[1].SrcRegister.File = TGSI_FILE_IMMEDIATE;
newInst.FullSrcRegisters[1].SrcRegister.Index = pctx->numImmed;
newInst.Src[0].Register.File = TGSI_FILE_INPUT;
newInst.Src[0].Register.Index = wincoordInput;
newInst.Src[1].Register.File = TGSI_FILE_IMMEDIATE;
newInst.Src[1].Register.Index = pctx->numImmed;
ctx->emit_instruction(ctx, &newInst);
/* TEX texTemp, texTemp, sampler; */
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_TEX;
newInst.Instruction.NumDstRegs = 1;
newInst.FullDstRegisters[0].DstRegister.File = TGSI_FILE_TEMPORARY;
newInst.FullDstRegisters[0].DstRegister.Index = pctx->texTemp;
newInst.Dst[0].Register.File = TGSI_FILE_TEMPORARY;
newInst.Dst[0].Register.Index = pctx->texTemp;
newInst.Instruction.NumSrcRegs = 2;
newInst.InstructionExtTexture.Texture = TGSI_TEXTURE_2D;
newInst.FullSrcRegisters[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
newInst.FullSrcRegisters[0].SrcRegister.Index = pctx->texTemp;
newInst.FullSrcRegisters[1].SrcRegister.File = TGSI_FILE_SAMPLER;
newInst.FullSrcRegisters[1].SrcRegister.Index = pctx->freeSampler;
newInst.Instruction.Texture = TRUE;
newInst.Texture.Texture = TGSI_TEXTURE_2D;
newInst.Src[0].Register.File = TGSI_FILE_TEMPORARY;
newInst.Src[0].Register.Index = pctx->texTemp;
newInst.Src[1].Register.File = TGSI_FILE_SAMPLER;
newInst.Src[1].Register.Index = pctx->freeSampler;
ctx->emit_instruction(ctx, &newInst);
/* KIL -texTemp; # if -texTemp < 0, KILL fragment */
@ -308,9 +309,9 @@ pstip_transform_inst(struct tgsi_transform_context *ctx,
newInst.Instruction.Opcode = TGSI_OPCODE_KIL;
newInst.Instruction.NumDstRegs = 0;
newInst.Instruction.NumSrcRegs = 1;
newInst.FullSrcRegisters[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
newInst.FullSrcRegisters[0].SrcRegister.Index = pctx->texTemp;
newInst.FullSrcRegisters[0].SrcRegister.Negate = 1;
newInst.Src[0].Register.File = TGSI_FILE_TEMPORARY;
newInst.Src[0].Register.Index = pctx->texTemp;
newInst.Src[0].Register.Negate = 1;
ctx->emit_instruction(ctx, &newInst);
}

220
src/gallium/auxiliary/draw/draw_vs_aos.c
View file

@ -361,8 +361,8 @@ static struct x86_reg aos_get_shader_reg_ptr( struct aos_compilation *cp,
static struct x86_reg get_dst_ptr( struct aos_compilation *cp,
const struct tgsi_full_dst_register *dst )
{
unsigned file = dst->DstRegister.File;
unsigned idx = dst->DstRegister.Index;
unsigned file = dst->Register.File;
unsigned idx = dst->Register.Index;
unsigned i;
@ -529,8 +529,8 @@ static struct x86_reg fetch_src( struct aos_compilation *cp,
const struct tgsi_full_src_register *src )
{
struct x86_reg arg0 = aos_get_shader_reg(cp,
src->SrcRegister.File,
src->SrcRegister.Index);
src->Register.File,
src->Register.Index);
unsigned i;
ubyte swz = 0;
unsigned negs = 0;
@ -620,8 +620,8 @@ static void x87_fld_src( struct aos_compilation *cp,
unsigned channel )
{
struct x86_reg arg0 = aos_get_shader_reg_ptr(cp,
src->SrcRegister.File,
src->SrcRegister.Index);
src->Register.File,
src->Register.Index);
unsigned swizzle = tgsi_util_get_full_src_register_swizzle( src, channel );
unsigned neg = tgsi_util_get_full_src_register_sign_mode( src, channel );
@ -669,15 +669,15 @@ static void store_dest( struct aos_compilation *cp,
{
struct x86_reg dst;
switch (reg->DstRegister.WriteMask) {
switch (reg->Register.WriteMask) {
case 0:
return;
case TGSI_WRITEMASK_XYZW:
aos_adopt_xmm_reg(cp,
get_xmm_writable(cp, result),
reg->DstRegister.File,
reg->DstRegister.Index,
reg->Register.File,
reg->Register.Index,
TRUE);
return;
default:
@ -685,10 +685,10 @@ static void store_dest( struct aos_compilation *cp,
}
dst = aos_get_shader_reg_xmm(cp,
reg->DstRegister.File,
reg->DstRegister.Index);
reg->Register.File,
reg->Register.Index);
switch (reg->DstRegister.WriteMask) {
switch (reg->Register.WriteMask) {
case TGSI_WRITEMASK_X:
sse_movss(cp->func, dst, get_xmm(cp, result));
break;
@ -710,14 +710,14 @@ static void store_dest( struct aos_compilation *cp,
break;
default:
mask_write(cp, dst, result, reg->DstRegister.WriteMask);
mask_write(cp, dst, result, reg->Register.WriteMask);
break;
}
aos_adopt_xmm_reg(cp,
dst,
reg->DstRegister.File,
reg->DstRegister.Index,
reg->Register.File,
reg->Register.Index,
TRUE);
}
@ -737,7 +737,7 @@ static void store_scalar_dest( struct aos_compilation *cp,
const struct tgsi_full_dst_register *reg,
struct x86_reg result )
{
unsigned writemask = reg->DstRegister.WriteMask;
unsigned writemask = reg->Register.WriteMask;
struct x86_reg dst;
if (writemask != TGSI_WRITEMASK_X &&
@ -754,12 +754,12 @@ static void store_scalar_dest( struct aos_compilation *cp,
result = get_xmm(cp, result);
dst = aos_get_shader_reg_xmm(cp,
reg->DstRegister.File,
reg->DstRegister.Index);
reg->Register.File,
reg->Register.Index);
switch (reg->DstRegister.WriteMask) {
switch (reg->Register.WriteMask) {
case TGSI_WRITEMASK_X:
sse_movss(cp->func, dst, result);
break;
@ -782,8 +782,8 @@ static void store_scalar_dest( struct aos_compilation *cp,
aos_adopt_xmm_reg(cp,
dst,
reg->DstRegister.File,
reg->DstRegister.Index,
reg->Register.File,
reg->Register.Index,
TRUE);
}
@ -819,7 +819,7 @@ static void x87_fstp_dest4( struct aos_compilation *cp,
const struct tgsi_full_dst_register *dst )
{
struct x86_reg ptr = get_dst_ptr(cp, dst);
unsigned writemask = dst->DstRegister.WriteMask;
unsigned writemask = dst->Register.WriteMask;
x87_fst_or_nop(cp->func, writemask, 0, ptr);
x87_fst_or_nop(cp->func, writemask, 1, ptr);
@ -956,7 +956,7 @@ static void emit_print( struct aos_compilation *cp,
static boolean emit_ABS( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
struct x86_reg arg0 = fetch_src(cp, &op->FullSrcRegisters[0]);
struct x86_reg arg0 = fetch_src(cp, &op->Src[0]);
struct x86_reg neg = aos_get_internal(cp, IMM_NEGS);
struct x86_reg tmp = aos_get_xmm_reg(cp);
@ -964,27 +964,27 @@ static boolean emit_ABS( struct aos_compilation *cp, const struct tgsi_full_inst
sse_mulps(cp->func, tmp, neg);
sse_maxps(cp->func, tmp, arg0);
store_dest(cp, &op->FullDstRegisters[0], tmp);
store_dest(cp, &op->Dst[0], tmp);
return TRUE;
}
static boolean emit_ADD( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
struct x86_reg arg0 = fetch_src(cp, &op->FullSrcRegisters[0]);
struct x86_reg arg1 = fetch_src(cp, &op->FullSrcRegisters[1]);
struct x86_reg arg0 = fetch_src(cp, &op->Src[0]);
struct x86_reg arg1 = fetch_src(cp, &op->Src[1]);
struct x86_reg dst = get_xmm_writable(cp, arg0);
sse_addps(cp->func, dst, arg1);
store_dest(cp, &op->FullDstRegisters[0], dst);
store_dest(cp, &op->Dst[0], dst);
return TRUE;
}
static boolean emit_COS( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
x87_fld_src(cp, &op->FullSrcRegisters[0], 0);
x87_fld_src(cp, &op->Src[0], 0);
x87_fcos(cp->func);
x87_fstp_dest4(cp, &op->FullDstRegisters[0]);
x87_fstp_dest4(cp, &op->Dst[0]);
return TRUE;
}
@ -993,8 +993,8 @@ static boolean emit_COS( struct aos_compilation *cp, const struct tgsi_full_inst
*/
static boolean emit_DP3( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
struct x86_reg arg0 = fetch_src(cp, &op->FullSrcRegisters[0]);
struct x86_reg arg1 = fetch_src(cp, &op->FullSrcRegisters[1]);
struct x86_reg arg0 = fetch_src(cp, &op->Src[0]);
struct x86_reg arg1 = fetch_src(cp, &op->Src[1]);
struct x86_reg tmp = aos_get_xmm_reg(cp);
struct x86_reg dst = get_xmm_writable(cp, arg0);
@ -1007,14 +1007,14 @@ static boolean emit_DP3( struct aos_compilation *cp, const struct tgsi_full_inst
sse_addss(cp->func, dst, tmp);
aos_release_xmm_reg(cp, tmp.idx);
store_scalar_dest(cp, &op->FullDstRegisters[0], dst);
store_scalar_dest(cp, &op->Dst[0], dst);
return TRUE;
}
static boolean emit_DP4( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
struct x86_reg arg0 = fetch_src(cp, &op->FullSrcRegisters[0]);
struct x86_reg arg1 = fetch_src(cp, &op->FullSrcRegisters[1]);
struct x86_reg arg0 = fetch_src(cp, &op->Src[0]);
struct x86_reg arg1 = fetch_src(cp, &op->Src[1]);
struct x86_reg tmp = aos_get_xmm_reg(cp);
struct x86_reg dst = get_xmm_writable(cp, arg0);
@ -1028,14 +1028,14 @@ static boolean emit_DP4( struct aos_compilation *cp, const struct tgsi_full_inst
sse_addss(cp->func, dst, tmp);
aos_release_xmm_reg(cp, tmp.idx);
store_scalar_dest(cp, &op->FullDstRegisters[0], dst);
store_scalar_dest(cp, &op->Dst[0], dst);
return TRUE;
}
static boolean emit_DPH( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
struct x86_reg arg0 = fetch_src(cp, &op->FullSrcRegisters[0]);
struct x86_reg arg1 = fetch_src(cp, &op->FullSrcRegisters[1]);
struct x86_reg arg0 = fetch_src(cp, &op->Src[0]);
struct x86_reg arg1 = fetch_src(cp, &op->Src[1]);
struct x86_reg tmp = aos_get_xmm_reg(cp);
struct x86_reg dst = get_xmm_writable(cp, arg0);
@ -1051,14 +1051,14 @@ static boolean emit_DPH( struct aos_compilation *cp, const struct tgsi_full_inst
sse_addss(cp->func, dst, tmp);
aos_release_xmm_reg(cp, tmp.idx);
store_scalar_dest(cp, &op->FullDstRegisters[0], dst);
store_scalar_dest(cp, &op->Dst[0], dst);
return TRUE;
}
static boolean emit_DST( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
struct x86_reg arg0 = fetch_src(cp, &op->FullSrcRegisters[0]);
struct x86_reg arg1 = fetch_src(cp, &op->FullSrcRegisters[1]);
struct x86_reg arg0 = fetch_src(cp, &op->Src[0]);
struct x86_reg arg1 = fetch_src(cp, &op->Src[1]);
struct x86_reg dst = aos_get_xmm_reg(cp);
struct x86_reg tmp = aos_get_xmm_reg(cp);
struct x86_reg ones = aos_get_internal(cp, IMM_ONES);
@ -1073,25 +1073,25 @@ static boolean emit_DST( struct aos_compilation *cp, const struct tgsi_full_inst
sse_mulps(cp->func, dst, tmp);
aos_release_xmm_reg(cp, tmp.idx);
store_dest(cp, &op->FullDstRegisters[0], dst);
store_dest(cp, &op->Dst[0], dst);
return TRUE;
}
static boolean emit_LG2( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
x87_fld1(cp->func); /* 1 */
x87_fld_src(cp, &op->FullSrcRegisters[0], 0); /* a0 1 */
x87_fld_src(cp, &op->Src[0], 0); /* a0 1 */
x87_fyl2x(cp->func); /* log2(a0) */
x87_fstp_dest4(cp, &op->FullDstRegisters[0]);
x87_fstp_dest4(cp, &op->Dst[0]);
return TRUE;
}
#if 0
static boolean emit_EX2( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
x87_fld_src(cp, &op->FullSrcRegisters[0], 0);
x87_fld_src(cp, &op->Src[0], 0);
x87_emit_ex2(cp);
x87_fstp_dest4(cp, &op->FullDstRegisters[0]);
x87_fstp_dest4(cp, &op->Dst[0]);
return TRUE;
}
#endif
@ -1099,8 +1099,8 @@ static boolean emit_EX2( struct aos_compilation *cp, const struct tgsi_full_inst
static boolean emit_FLR( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
struct x86_reg dst = get_dst_ptr(cp, &op->FullDstRegisters[0]);
unsigned writemask = op->FullDstRegisters[0].DstRegister.WriteMask;
struct x86_reg dst = get_dst_ptr(cp, &op->Dst[0]);
unsigned writemask = op->Dst[0].Register.WriteMask;
int i;
set_fpu_round_neg_inf( cp );
@ -1109,7 +1109,7 @@ static boolean emit_FLR( struct aos_compilation *cp, const struct tgsi_full_inst
*/
for (i = 3; i >= 0; i--) {
if (writemask & (1<<i)) {
x87_fld_src(cp, &op->FullSrcRegisters[0], i);
x87_fld_src(cp, &op->Src[0], i);
}
}
@ -1126,8 +1126,8 @@ static boolean emit_FLR( struct aos_compilation *cp, const struct tgsi_full_inst
static boolean emit_RND( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
struct x86_reg dst = get_dst_ptr(cp, &op->FullDstRegisters[0]);
unsigned writemask = op->FullDstRegisters[0].DstRegister.WriteMask;
struct x86_reg dst = get_dst_ptr(cp, &op->Dst[0]);
unsigned writemask = op->Dst[0].Register.WriteMask;
int i;
set_fpu_round_nearest( cp );
@ -1136,7 +1136,7 @@ static boolean emit_RND( struct aos_compilation *cp, const struct tgsi_full_inst
*/
for (i = 3; i >= 0; i--) {
if (writemask & (1<<i)) {
x87_fld_src(cp, &op->FullSrcRegisters[0], i);
x87_fld_src(cp, &op->Src[0], i);
}
}
@ -1153,10 +1153,10 @@ static boolean emit_RND( struct aos_compilation *cp, const struct tgsi_full_inst
static boolean emit_FRC( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
struct x86_reg dst = get_dst_ptr(cp, &op->FullDstRegisters[0]);
struct x86_reg dst = get_dst_ptr(cp, &op->Dst[0]);
struct x86_reg st0 = x86_make_reg(file_x87, 0);
struct x86_reg st1 = x86_make_reg(file_x87, 1);
unsigned writemask = op->FullDstRegisters[0].DstRegister.WriteMask;
unsigned writemask = op->Dst[0].Register.WriteMask;
int i;
set_fpu_round_neg_inf( cp );
@ -1166,7 +1166,7 @@ static boolean emit_FRC( struct aos_compilation *cp, const struct tgsi_full_inst
*/
for (i = 3; i >= 0; i--) {
if (writemask & (1<<i)) {
x87_fld_src(cp, &op->FullSrcRegisters[0], i);
x87_fld_src(cp, &op->Src[0], i);
}
}
@ -1190,7 +1190,7 @@ static boolean emit_FRC( struct aos_compilation *cp, const struct tgsi_full_inst
static boolean emit_LIT( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
struct x86_reg ecx = x86_make_reg( file_REG32, reg_CX );
unsigned writemask = op->FullDstRegisters[0].DstRegister.WriteMask;
unsigned writemask = op->Dst[0].Register.WriteMask;
unsigned lit_count = cp->lit_count++;
struct x86_reg result, arg0;
unsigned i;
@ -1209,10 +1209,10 @@ static boolean emit_LIT( struct aos_compilation *cp, const struct tgsi_full_inst
if (writemask != TGSI_WRITEMASK_XYZW)
result = x86_make_disp(cp->machine_EDX, Offset(struct aos_machine, tmp[0]));
else
result = get_dst_ptr(cp, &op->FullDstRegisters[0]);
result = get_dst_ptr(cp, &op->Dst[0]);
arg0 = fetch_src( cp, &op->FullSrcRegisters[0] );
arg0 = fetch_src( cp, &op->Src[0] );
if (arg0.file == file_XMM) {
struct x86_reg tmp = x86_make_disp(cp->machine_EDX,
Offset(struct aos_machine, tmp[1]));
@ -1259,7 +1259,7 @@ static boolean emit_LIT( struct aos_compilation *cp, const struct tgsi_full_inst
if (writemask != TGSI_WRITEMASK_XYZW) {
store_dest( cp,
&op->FullDstRegisters[0],
&op->Dst[0],
get_xmm_writable( cp, result ) );
}
@ -1269,8 +1269,8 @@ static boolean emit_LIT( struct aos_compilation *cp, const struct tgsi_full_inst
#if 0
static boolean emit_inline_LIT( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
struct x86_reg dst = get_dst_ptr(cp, &op->FullDstRegisters[0]);
unsigned writemask = op->FullDstRegisters[0].DstRegister.WriteMask;
struct x86_reg dst = get_dst_ptr(cp, &op->Dst[0]);
unsigned writemask = op->Dst[0].Register.WriteMask;
if (writemask & TGSI_WRITEMASK_YZ) {
struct x86_reg st1 = x86_make_reg(file_x87, 1);
@ -1286,13 +1286,13 @@ static boolean emit_inline_LIT( struct aos_compilation *cp, const struct tgsi_fu
*/
x87_fldz(cp->func); /* 1 0 */
#endif
x87_fld_src(cp, &op->FullSrcRegisters[0], 1); /* a1 1 0 */
x87_fld_src(cp, &op->Src[0], 1); /* a1 1 0 */
x87_fcomi(cp->func, st2); /* a1 1 0 */
x87_fcmovb(cp->func, st1); /* a1' 1 0 */
x87_fstp(cp->func, st1); /* a1' 0 */
x87_fstp(cp->func, st1); /* a1' */
x87_fld_src(cp, &op->FullSrcRegisters[0], 3); /* a3 a1' */
x87_fld_src(cp, &op->Src[0], 3); /* a3 a1' */
x87_fxch(cp->func, st1); /* a1' a3 */
@ -1305,7 +1305,7 @@ static boolean emit_inline_LIT( struct aos_compilation *cp, const struct tgsi_fu
/* a0' = max2(a0, 0):
*/
x87_fldz(cp->func); /* 0 r2 */
x87_fld_src(cp, &op->FullSrcRegisters[0], 0); /* a0 0 r2 */
x87_fld_src(cp, &op->Src[0], 0); /* a0 0 r2 */
x87_fcomi(cp->func, st1);
x87_fcmovb(cp->func, st1); /* a0' 0 r2 */
@ -1333,58 +1333,58 @@ static boolean emit_inline_LIT( struct aos_compilation *cp, const struct tgsi_fu
static boolean emit_MAX( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
struct x86_reg arg0 = fetch_src(cp, &op->FullSrcRegisters[0]);
struct x86_reg arg1 = fetch_src(cp, &op->FullSrcRegisters[1]);
struct x86_reg arg0 = fetch_src(cp, &op->Src[0]);
struct x86_reg arg1 = fetch_src(cp, &op->Src[1]);
struct x86_reg dst = get_xmm_writable(cp, arg0);
sse_maxps(cp->func, dst, arg1);
store_dest(cp, &op->FullDstRegisters[0], dst);
store_dest(cp, &op->Dst[0], dst);
return TRUE;
}
static boolean emit_MIN( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
struct x86_reg arg0 = fetch_src(cp, &op->FullSrcRegisters[0]);
struct x86_reg arg1 = fetch_src(cp, &op->FullSrcRegisters[1]);
struct x86_reg arg0 = fetch_src(cp, &op->Src[0]);
struct x86_reg arg1 = fetch_src(cp, &op->Src[1]);
struct x86_reg dst = get_xmm_writable(cp, arg0);
sse_minps(cp->func, dst, arg1);
store_dest(cp, &op->FullDstRegisters[0], dst);
store_dest(cp, &op->Dst[0], dst);
return TRUE;
}
static boolean emit_MOV( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
struct x86_reg arg0 = fetch_src(cp, &op->FullSrcRegisters[0]);
struct x86_reg arg0 = fetch_src(cp, &op->Src[0]);
struct x86_reg dst = get_xmm_writable(cp, arg0);
/* potentially nothing to do */
store_dest(cp, &op->FullDstRegisters[0], dst);
store_dest(cp, &op->Dst[0], dst);
return TRUE;
}
static boolean emit_MUL( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
struct x86_reg arg0 = fetch_src(cp, &op->FullSrcRegisters[0]);
struct x86_reg arg1 = fetch_src(cp, &op->FullSrcRegisters[1]);
struct x86_reg arg0 = fetch_src(cp, &op->Src[0]);
struct x86_reg arg1 = fetch_src(cp, &op->Src[1]);
struct x86_reg dst = get_xmm_writable(cp, arg0);
sse_mulps(cp->func, dst, arg1);
store_dest(cp, &op->FullDstRegisters[0], dst);
store_dest(cp, &op->Dst[0], dst);
return TRUE;
}
static boolean emit_MAD( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
struct x86_reg arg0 = fetch_src(cp, &op->FullSrcRegisters[0]);
struct x86_reg arg1 = fetch_src(cp, &op->FullSrcRegisters[1]);
struct x86_reg arg2 = fetch_src(cp, &op->FullSrcRegisters[2]);
struct x86_reg arg0 = fetch_src(cp, &op->Src[0]);
struct x86_reg arg1 = fetch_src(cp, &op->Src[1]);
struct x86_reg arg2 = fetch_src(cp, &op->Src[2]);
/* If we can't clobber old contents of arg0, get a temporary & copy
* it there, then clobber it...
@ -1393,7 +1393,7 @@ static boolean emit_MAD( struct aos_compilation *cp, const struct tgsi_full_inst
sse_mulps(cp->func, arg0, arg1);
sse_addps(cp->func, arg0, arg2);
store_dest(cp, &op->FullDstRegisters[0], arg0);
store_dest(cp, &op->Dst[0], arg0);
return TRUE;
}
@ -1425,13 +1425,13 @@ static float PIPE_CDECL _exp2(float x)
static boolean emit_POW( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
#if 0
x87_fld_src(cp, &op->FullSrcRegisters[1], 0); /* a1.x */
x87_fld_src(cp, &op->FullSrcRegisters[0], 0); /* a0.x a1.x */
x87_fld_src(cp, &op->Src[1], 0); /* a1.x */
x87_fld_src(cp, &op->Src[0], 0); /* a0.x a1.x */
x87_fyl2x(cp->func); /* a1*log2(a0) */
x87_emit_ex2( cp ); /* 2^(a1*log2(a0)) */
x87_fstp_dest4(cp, &op->FullDstRegisters[0]);
x87_fstp_dest4(cp, &op->Dst[0]);
#else
uint i;
@ -1450,9 +1450,9 @@ static boolean emit_POW( struct aos_compilation *cp, const struct tgsi_full_inst
x86_lea( cp->func, cp->stack_ESP, x86_make_disp(cp->stack_ESP, -8) );
x87_fld_src( cp, &op->FullSrcRegisters[1], 0 );
x87_fld_src( cp, &op->Src[1], 0 );
x87_fstp( cp->func, x86_make_disp( cp->stack_ESP, 4 ) );
x87_fld_src( cp, &op->FullSrcRegisters[0], 0 );
x87_fld_src( cp, &op->Src[0], 0 );
x87_fstp( cp->func, x86_make_disp( cp->stack_ESP, 0 ) );
/* tmp_EAX has been pushed & will be restored below */
@ -1467,7 +1467,7 @@ static boolean emit_POW( struct aos_compilation *cp, const struct tgsi_full_inst
*/
cp->func->x87_stack++;
x87_fstp_dest4( cp, &op->FullDstRegisters[0] );
x87_fstp_dest4( cp, &op->Dst[0] );
#endif
return TRUE;
}
@ -1493,7 +1493,7 @@ static boolean emit_EXPBASE2( struct aos_compilation *cp, const struct tgsi_full
x86_lea( cp->func, cp->stack_ESP, x86_make_disp(cp->stack_ESP, -4) );
x87_fld_src( cp, &op->FullSrcRegisters[0], 0 );
x87_fld_src( cp, &op->Src[0], 0 );
x87_fstp( cp->func, x86_make_disp( cp->stack_ESP, 0 ) );
/* tmp_EAX has been pushed & will be restored below */
@ -1508,7 +1508,7 @@ static boolean emit_EXPBASE2( struct aos_compilation *cp, const struct tgsi_full
*/
cp->func->x87_stack++;
x87_fstp_dest4( cp, &op->FullDstRegisters[0] );
x87_fstp_dest4( cp, &op->Dst[0] );
return TRUE;
}
@ -1517,7 +1517,7 @@ static boolean emit_EXPBASE2( struct aos_compilation *cp, const struct tgsi_full
static boolean emit_RCP( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
struct x86_reg arg0 = fetch_src(cp, &op->FullSrcRegisters[0]);
struct x86_reg arg0 = fetch_src(cp, &op->Src[0]);
struct x86_reg dst = aos_get_xmm_reg(cp);
if (cp->have_sse2) {
@ -1531,7 +1531,7 @@ static boolean emit_RCP( struct aos_compilation *cp, const struct tgsi_full_inst
sse_divss(cp->func, dst, arg0);
}
store_scalar_dest(cp, &op->FullDstRegisters[0], dst);
store_scalar_dest(cp, &op->Dst[0], dst);
return TRUE;
}
@ -1551,14 +1551,14 @@ static boolean emit_RCP( struct aos_compilation *cp, const struct tgsi_full_inst
static boolean emit_RSQ( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
if (0) {
struct x86_reg arg0 = fetch_src(cp, &op->FullSrcRegisters[0]);
struct x86_reg arg0 = fetch_src(cp, &op->Src[0]);
struct x86_reg r = aos_get_xmm_reg(cp);
sse_rsqrtss(cp->func, r, arg0);
store_scalar_dest(cp, &op->FullDstRegisters[0], r);
store_scalar_dest(cp, &op->Dst[0], r);
return TRUE;
}
else {
struct x86_reg arg0 = fetch_src(cp, &op->FullSrcRegisters[0]);
struct x86_reg arg0 = fetch_src(cp, &op->Src[0]);
struct x86_reg r = aos_get_xmm_reg(cp);
struct x86_reg neg_half = get_reg_ptr( cp, AOS_FILE_INTERNAL, IMM_RSQ );
@ -1578,7 +1578,7 @@ static boolean emit_RSQ( struct aos_compilation *cp, const struct tgsi_full_inst
sse_addss( cp->func, tmp, one_point_five ); /* 1.5 - .5 * a * r * r */
sse_mulss( cp->func, r, tmp ); /* r * (1.5 - .5 * a * r * r) */
store_scalar_dest(cp, &op->FullDstRegisters[0], r);
store_scalar_dest(cp, &op->Dst[0], r);
aos_release_xmm_reg(cp, tmp.idx);
@ -1589,23 +1589,23 @@ static boolean emit_RSQ( struct aos_compilation *cp, const struct tgsi_full_inst
static boolean emit_SGE( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
struct x86_reg arg0 = fetch_src(cp, &op->FullSrcRegisters[0]);
struct x86_reg arg1 = fetch_src(cp, &op->FullSrcRegisters[1]);
struct x86_reg arg0 = fetch_src(cp, &op->Src[0]);
struct x86_reg arg1 = fetch_src(cp, &op->Src[1]);
struct x86_reg ones = aos_get_internal(cp, IMM_ONES);
struct x86_reg dst = get_xmm_writable(cp, arg0);
sse_cmpps(cp->func, dst, arg1, cc_NotLessThan);
sse_andps(cp->func, dst, ones);
store_dest(cp, &op->FullDstRegisters[0], dst);
store_dest(cp, &op->Dst[0], dst);
return TRUE;
}
static boolean emit_SIN( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
x87_fld_src(cp, &op->FullSrcRegisters[0], 0);
x87_fld_src(cp, &op->Src[0], 0);
x87_fsin(cp->func);
x87_fstp_dest4(cp, &op->FullDstRegisters[0]);
x87_fstp_dest4(cp, &op->Dst[0]);
return TRUE;
}
@ -1613,46 +1613,46 @@ static boolean emit_SIN( struct aos_compilation *cp, const struct tgsi_full_inst
static boolean emit_SLT( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
struct x86_reg arg0 = fetch_src(cp, &op->FullSrcRegisters[0]);
struct x86_reg arg1 = fetch_src(cp, &op->FullSrcRegisters[1]);
struct x86_reg arg0 = fetch_src(cp, &op->Src[0]);
struct x86_reg arg1 = fetch_src(cp, &op->Src[1]);
struct x86_reg ones = aos_get_internal(cp, IMM_ONES);
struct x86_reg dst = get_xmm_writable(cp, arg0);
sse_cmpps(cp->func, dst, arg1, cc_LessThan);
sse_andps(cp->func, dst, ones);
store_dest(cp, &op->FullDstRegisters[0], dst);
store_dest(cp, &op->Dst[0], dst);
return TRUE;
}
static boolean emit_SUB( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
struct x86_reg arg0 = fetch_src(cp, &op->FullSrcRegisters[0]);
struct x86_reg arg1 = fetch_src(cp, &op->FullSrcRegisters[1]);
struct x86_reg arg0 = fetch_src(cp, &op->Src[0]);
struct x86_reg arg1 = fetch_src(cp, &op->Src[1]);
struct x86_reg dst = get_xmm_writable(cp, arg0);
sse_subps(cp->func, dst, arg1);
store_dest(cp, &op->FullDstRegisters[0], dst);
store_dest(cp, &op->Dst[0], dst);
return TRUE;
}
static boolean emit_TRUNC( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
struct x86_reg arg0 = fetch_src(cp, &op->FullSrcRegisters[0]);
struct x86_reg arg0 = fetch_src(cp, &op->Src[0]);
struct x86_reg tmp0 = aos_get_xmm_reg(cp);
sse2_cvttps2dq(cp->func, tmp0, arg0);
sse2_cvtdq2ps(cp->func, tmp0, tmp0);
store_dest(cp, &op->FullDstRegisters[0], tmp0);
store_dest(cp, &op->Dst[0], tmp0);
return TRUE;
}
static boolean emit_XPD( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
struct x86_reg arg0 = fetch_src(cp, &op->FullSrcRegisters[0]);
struct x86_reg arg1 = fetch_src(cp, &op->FullSrcRegisters[1]);
struct x86_reg arg0 = fetch_src(cp, &op->Src[0]);
struct x86_reg arg1 = fetch_src(cp, &op->Src[1]);
struct x86_reg tmp0 = aos_get_xmm_reg(cp);
struct x86_reg tmp1 = aos_get_xmm_reg(cp);
@ -1670,7 +1670,7 @@ static boolean emit_XPD( struct aos_compilation *cp, const struct tgsi_full_inst
aos_release_xmm_reg(cp, tmp0.idx);
store_dest(cp, &op->FullDstRegisters[0], tmp1);
store_dest(cp, &op->Dst[0], tmp1);
return TRUE;
}
@ -1897,10 +1897,10 @@ static void find_last_write_outputs( struct aos_compilation *cp )
continue;
for (i = 0; i < TGSI_FULL_MAX_DST_REGISTERS; i++) {
if (parse.FullToken.FullInstruction.FullDstRegisters[i].DstRegister.File ==
if (parse.FullToken.FullInstruction.Dst[i].Register.File ==
TGSI_FILE_OUTPUT)
{
unsigned idx = parse.FullToken.FullInstruction.FullDstRegisters[i].DstRegister.Index;
unsigned idx = parse.FullToken.FullInstruction.Dst[i].Register.Index;
cp->output_last_write[idx] = this_instruction;
}
}

64
src/gallium/auxiliary/gallivm/tgsitollvm.cpp
View file

@ -94,8 +94,8 @@ translate_declaration(struct gallivm_ir *prog,
unsigned first, last, mask;
uint interp_method;
first = decl->DeclarationRange.First;
last = decl->DeclarationRange.Last;
first = decl->Range.First;
last = decl->Range.Last;
mask = decl->Declaration.UsageMask;
/* Do not touch WPOS.xy */
@ -149,7 +149,7 @@ translate_declarationir(struct gallivm_ir *,
struct tgsi_full_declaration *)
{
if (decl->Declaration.File == TGSI_FILE_ADDRESS) {
int idx = decl->DeclarationRange.First;
int idx = decl->Range.First;
storage->addAddress(idx);
}
}
@ -234,26 +234,26 @@ translate_instruction(llvm::Module *module,
inputs[3] = 0;
for (int i = 0; i < inst->Instruction.NumSrcRegs; ++i) {
struct tgsi_full_src_register *src = &inst->FullSrcRegisters[i];
struct tgsi_full_src_register *src = &inst->Src[i];
llvm::Value *val = 0;
llvm::Value *indIdx = 0;
if (src->SrcRegister.Indirect) {
indIdx = storage->addrElement(src->SrcRegisterInd.Index);
if (src->Register.Indirect) {
indIdx = storage->addrElement(src->Indirect.Index);
indIdx = storage->extractIndex(indIdx);
}
if (src->SrcRegister.File == TGSI_FILE_CONSTANT) {
val = storage->constElement(src->SrcRegister.Index, indIdx);
} else if (src->SrcRegister.File == TGSI_FILE_INPUT) {
val = storage->inputElement(src->SrcRegister.Index, indIdx);
} else if (src->SrcRegister.File == TGSI_FILE_TEMPORARY) {
val = storage->tempElement(src->SrcRegister.Index);
} else if (src->SrcRegister.File == TGSI_FILE_OUTPUT) {
val = storage->outputElement(src->SrcRegister.Index, indIdx);
} else if (src->SrcRegister.File == TGSI_FILE_IMMEDIATE) {
val = storage->immediateElement(src->SrcRegister.Index);
if (src->Register.File == TGSI_FILE_CONSTANT) {
val = storage->constElement(src->Register.Index, indIdx);
} else if (src->Register.File == TGSI_FILE_INPUT) {
val = storage->inputElement(src->Register.Index, indIdx);
} else if (src->Register.File == TGSI_FILE_TEMPORARY) {
val = storage->tempElement(src->Register.Index);
} else if (src->Register.File == TGSI_FILE_OUTPUT) {
val = storage->outputElement(src->Register.Index, indIdx);
} else if (src->Register.File == TGSI_FILE_IMMEDIATE) {
val = storage->immediateElement(src->Register.Index);
} else {
fprintf(stderr, "ERROR: not supported llvm source %d\n", src->SrcRegister.File);
fprintf(stderr, "ERROR: not supported llvm source %d\n", src->Register.File);
return;
}
@ -656,14 +656,14 @@ translate_instruction(llvm::Module *module,
/* store results */
for (int i = 0; i < inst->Instruction.NumDstRegs; ++i) {
struct tgsi_full_dst_register *dst = &inst->FullDstRegisters[i];
struct tgsi_full_dst_register *dst = &inst->Dst[i];
if (dst->DstRegister.File == TGSI_FILE_OUTPUT) {
storage->setOutputElement(dst->DstRegister.Index, out, dst->DstRegister.WriteMask);
} else if (dst->DstRegister.File == TGSI_FILE_TEMPORARY) {
storage->setTempElement(dst->DstRegister.Index, out, dst->DstRegister.WriteMask);
} else if (dst->DstRegister.File == TGSI_FILE_ADDRESS) {
storage->setAddrElement(dst->DstRegister.Index, out, dst->DstRegister.WriteMask);
if (dst->Register.File == TGSI_FILE_OUTPUT) {
storage->setOutputElement(dst->Register.Index, out, dst->Register.WriteMask);
} else if (dst->Register.File == TGSI_FILE_TEMPORARY) {
storage->setTempElement(dst->Register.Index, out, dst->Register.WriteMask);
} else if (dst->Register.File == TGSI_FILE_ADDRESS) {
storage->setAddrElement(dst->Register.Index, out, dst->Register.WriteMask);
} else {
fprintf(stderr, "ERROR: unsupported LLVM destination!");
assert(!"wrong destination");
@ -683,16 +683,16 @@ translate_instructionir(llvm::Module *module,
std::vector< std::vector<llvm::Value*> > inputs(inst->Instruction.NumSrcRegs);
for (int i = 0; i < inst->Instruction.NumSrcRegs; ++i) {
struct tgsi_full_src_register *src = &inst->FullSrcRegisters[i];
struct tgsi_full_src_register *src = &inst->Src[i];
std::vector<llvm::Value*> val;
llvm::Value *indIdx = 0;
int swizzle = swizzleInt(src);
if (src->SrcRegister.Indirect) {
indIdx = storage->addrElement(src->SrcRegisterInd.Index);
if (src->Register.Indirect) {
indIdx = storage->addrElement(src->Indirect.Index);
}
val = storage->load((enum tgsi_file_type)src->SrcRegister.File,
src->SrcRegister.Index, swizzle, instr->getIRBuilder(), indIdx);
val = storage->load((enum tgsi_file_type)src->Register.File,
src->Register.Index, swizzle, instr->getIRBuilder(), indIdx);
inputs[i] = val;
}
@ -993,9 +993,9 @@ translate_instructionir(llvm::Module *module,
/* store results */
for (int i = 0; i < inst->Instruction.NumDstRegs; ++i) {
struct tgsi_full_dst_register *dst = &inst->FullDstRegisters[i];
storage->store((enum tgsi_file_type)dst->DstRegister.File,
dst->DstRegister.Index, out, dst->DstRegister.WriteMask,
struct tgsi_full_dst_register *dst = &inst->Dst[i];
storage->store((enum tgsi_file_type)dst->Register.File,
dst->Register.Index, out, dst->Register.WriteMask,
instr->getIRBuilder() );
}
}

447
src/gallium/auxiliary/tgsi/tgsi_build.c
View file

@ -30,21 +30,6 @@
#include "tgsi_build.h"
#include "tgsi_parse.h"
/*
* version
*/
struct tgsi_version
tgsi_build_version( void )
{
struct tgsi_version version;
version.MajorVersion = 1;
version.MinorVersion = 1;
version.Padding = 0;
return version;
}
/*
* header
@ -122,7 +107,6 @@ tgsi_default_declaration( void )
declaration.Centroid = 0;
declaration.Invariant = 0;
declaration.Padding = 0;
declaration.Extended = 0;
return declaration;
}
@ -173,7 +157,7 @@ tgsi_default_full_declaration( void )
struct tgsi_full_declaration full_declaration;
full_declaration.Declaration = tgsi_default_declaration();
full_declaration.DeclarationRange = tgsi_default_declaration_range();
full_declaration.Range = tgsi_default_declaration_range();
full_declaration.Semantic = tgsi_default_declaration_semantic();
return full_declaration;
@ -210,8 +194,8 @@ tgsi_build_full_declaration(
size++;
*dr = tgsi_build_declaration_range(
full_decl->DeclarationRange.First,
full_decl->DeclarationRange.Last,
full_decl->Range.First,
full_decl->Range.Last,
declaration,
header );
@ -224,8 +208,8 @@ tgsi_build_full_declaration(
size++;
*ds = tgsi_build_declaration_semantic(
full_decl->Semantic.SemanticName,
full_decl->Semantic.SemanticIndex,
full_decl->Semantic.Name,
full_decl->Semantic.Index,
declaration,
header );
}
@ -270,8 +254,8 @@ tgsi_default_declaration_semantic( void )
{
struct tgsi_declaration_semantic ds;
ds.SemanticName = TGSI_SEMANTIC_POSITION;
ds.SemanticIndex = 0;
ds.Name = TGSI_SEMANTIC_POSITION;
ds.Index = 0;
ds.Padding = 0;
return ds;
@ -290,8 +274,8 @@ tgsi_build_declaration_semantic(
assert( semantic_index <= 0xFFFF );
ds = tgsi_default_declaration_semantic();
ds.SemanticName = semantic_name;
ds.SemanticIndex = semantic_index;
ds.Name = semantic_name;
ds.Index = semantic_index;
declaration_grow( declaration, header );
@ -311,7 +295,6 @@ tgsi_default_immediate( void )
immediate.NrTokens = 1;
immediate.DataType = TGSI_IMM_FLOAT32;
immediate.Padding = 0;
immediate.Extended = 0;
return immediate;
}
@ -422,8 +405,9 @@ tgsi_default_instruction( void )
instruction.Predicate = 0;
instruction.NumDstRegs = 1;
instruction.NumSrcRegs = 1;
instruction.Label = 0;
instruction.Texture = 0;
instruction.Padding = 0;
instruction.Extended = 0;
return instruction;
}
@ -474,18 +458,16 @@ tgsi_default_full_instruction( void )
unsigned i;
full_instruction.Instruction = tgsi_default_instruction();
full_instruction.InstructionPredicate = tgsi_default_instruction_predicate();
full_instruction.InstructionExtLabel = tgsi_default_instruction_ext_label();
full_instruction.InstructionExtTexture = tgsi_default_instruction_ext_texture();
full_instruction.Predicate = tgsi_default_instruction_predicate();
full_instruction.Label = tgsi_default_instruction_label();
full_instruction.Texture = tgsi_default_instruction_texture();
for( i = 0; i < TGSI_FULL_MAX_DST_REGISTERS; i++ ) {
full_instruction.FullDstRegisters[i] = tgsi_default_full_dst_register();
full_instruction.Dst[i] = tgsi_default_full_dst_register();
}
for( i = 0; i < TGSI_FULL_MAX_SRC_REGISTERS; i++ ) {
full_instruction.FullSrcRegisters[i] = tgsi_default_full_src_register();
full_instruction.Src[i] = tgsi_default_full_src_register();
}
full_instruction.Flags = 0x0;
return full_instruction;
}
@ -524,56 +506,52 @@ tgsi_build_full_instruction(
size++;
*instruction_predicate =
tgsi_build_instruction_predicate(full_inst->InstructionPredicate.Index,
full_inst->InstructionPredicate.Negate,
full_inst->InstructionPredicate.SwizzleX,
full_inst->InstructionPredicate.SwizzleY,
full_inst->InstructionPredicate.SwizzleZ,
full_inst->InstructionPredicate.SwizzleW,
tgsi_build_instruction_predicate(full_inst->Predicate.Index,
full_inst->Predicate.Negate,
full_inst->Predicate.SwizzleX,
full_inst->Predicate.SwizzleY,
full_inst->Predicate.SwizzleZ,
full_inst->Predicate.SwizzleW,
instruction,
header);
}
if( tgsi_compare_instruction_ext_label(
full_inst->InstructionExtLabel,
tgsi_default_instruction_ext_label() ) ) {
struct tgsi_instruction_ext_label *instruction_ext_label;
if (full_inst->Instruction.Label) {
struct tgsi_instruction_label *instruction_label;
if( maxsize <= size )
return 0;
instruction_ext_label =
(struct tgsi_instruction_ext_label *) &tokens[size];
instruction_label =
(struct tgsi_instruction_label *) &tokens[size];
size++;
*instruction_ext_label = tgsi_build_instruction_ext_label(
full_inst->InstructionExtLabel.Label,
*instruction_label = tgsi_build_instruction_label(
full_inst->Label.Label,
prev_token,
instruction,
header );
prev_token = (struct tgsi_token *) instruction_ext_label;
prev_token = (struct tgsi_token *) instruction_label;
}
if( tgsi_compare_instruction_ext_texture(
full_inst->InstructionExtTexture,
tgsi_default_instruction_ext_texture() ) ) {
struct tgsi_instruction_ext_texture *instruction_ext_texture;
if (full_inst->Instruction.Texture) {
struct tgsi_instruction_texture *instruction_texture;
if( maxsize <= size )
return 0;
instruction_ext_texture =
(struct tgsi_instruction_ext_texture *) &tokens[size];
instruction_texture =
(struct tgsi_instruction_texture *) &tokens[size];
size++;
*instruction_ext_texture = tgsi_build_instruction_ext_texture(
full_inst->InstructionExtTexture.Texture,
*instruction_texture = tgsi_build_instruction_texture(
full_inst->Texture.Texture,
prev_token,
instruction,
header );
prev_token = (struct tgsi_token *) instruction_ext_texture;
prev_token = (struct tgsi_token *) instruction_texture;
}
for( i = 0; i < full_inst->Instruction.NumDstRegs; i++ ) {
const struct tgsi_full_dst_register *reg = &full_inst->FullDstRegisters[i];
const struct tgsi_full_dst_register *reg = &full_inst->Dst[i];
struct tgsi_dst_register *dst_register;
struct tgsi_token *prev_token;
@ -583,34 +561,15 @@ tgsi_build_full_instruction(
size++;
*dst_register = tgsi_build_dst_register(
reg->DstRegister.File,
reg->DstRegister.WriteMask,
reg->DstRegister.Indirect,
reg->DstRegister.Index,
reg->Register.File,
reg->Register.WriteMask,
reg->Register.Indirect,
reg->Register.Index,
instruction,
header );
prev_token = (struct tgsi_token *) dst_register;
if( tgsi_compare_dst_register_ext_modulate(
reg->DstRegisterExtModulate,
tgsi_default_dst_register_ext_modulate() ) ) {
struct tgsi_dst_register_ext_modulate *dst_register_ext_modulate;
if( maxsize <= size )
return 0;
dst_register_ext_modulate =
(struct tgsi_dst_register_ext_modulate *) &tokens[size];
size++;
*dst_register_ext_modulate = tgsi_build_dst_register_ext_modulate(
reg->DstRegisterExtModulate.Modulate,
prev_token,
instruction,
header );
prev_token = (struct tgsi_token *) dst_register_ext_modulate;
}
if( reg->DstRegister.Indirect ) {
if( reg->Register.Indirect ) {
struct tgsi_src_register *ind;
if( maxsize <= size )
@ -619,22 +578,23 @@ tgsi_build_full_instruction(
size++;
*ind = tgsi_build_src_register(
reg->DstRegisterInd.File,
reg->DstRegisterInd.SwizzleX,
reg->DstRegisterInd.SwizzleY,
reg->DstRegisterInd.SwizzleZ,
reg->DstRegisterInd.SwizzleW,
reg->DstRegisterInd.Negate,
reg->DstRegisterInd.Indirect,
reg->DstRegisterInd.Dimension,
reg->DstRegisterInd.Index,
reg->Indirect.File,
reg->Indirect.SwizzleX,
reg->Indirect.SwizzleY,
reg->Indirect.SwizzleZ,
reg->Indirect.SwizzleW,
reg->Indirect.Negate,
reg->Indirect.Absolute,
reg->Indirect.Indirect,
reg->Indirect.Dimension,
reg->Indirect.Index,
instruction,
header );
}
}
for( i = 0; i < full_inst->Instruction.NumSrcRegs; i++ ) {
const struct tgsi_full_src_register *reg = &full_inst->FullSrcRegisters[i];
const struct tgsi_full_src_register *reg = &full_inst->Src[i];
struct tgsi_src_register *src_register;
struct tgsi_token *prev_token;
@ -644,43 +604,21 @@ tgsi_build_full_instruction(
size++;
*src_register = tgsi_build_src_register(
reg->SrcRegister.File,
reg->SrcRegister.SwizzleX,
reg->SrcRegister.SwizzleY,
reg->SrcRegister.SwizzleZ,
reg->SrcRegister.SwizzleW,
reg->SrcRegister.Negate,
reg->SrcRegister.Indirect,
reg->SrcRegister.Dimension,
reg->SrcRegister.Index,
reg->Register.File,
reg->Register.SwizzleX,
reg->Register.SwizzleY,
reg->Register.SwizzleZ,
reg->Register.SwizzleW,
reg->Register.Negate,
reg->Register.Absolute,
reg->Register.Indirect,
reg->Register.Dimension,
reg->Register.Index,
instruction,
header );
prev_token = (struct tgsi_token *) src_register;
if( tgsi_compare_src_register_ext_mod(
reg->SrcRegisterExtMod,
tgsi_default_src_register_ext_mod() ) ) {
struct tgsi_src_register_ext_mod *src_register_ext_mod;
if( maxsize <= size )
return 0;
src_register_ext_mod =
(struct tgsi_src_register_ext_mod *) &tokens[size];
size++;
*src_register_ext_mod = tgsi_build_src_register_ext_mod(
reg->SrcRegisterExtMod.Complement,
reg->SrcRegisterExtMod.Bias,
reg->SrcRegisterExtMod.Scale2X,
reg->SrcRegisterExtMod.Absolute,
reg->SrcRegisterExtMod.Negate,
prev_token,
instruction,
header );
prev_token = (struct tgsi_token *) src_register_ext_mod;
}
if( reg->SrcRegister.Indirect ) {
if( reg->Register.Indirect ) {
struct tgsi_src_register *ind;
if( maxsize <= size )
@ -689,23 +627,24 @@ tgsi_build_full_instruction(
size++;
*ind = tgsi_build_src_register(
reg->SrcRegisterInd.File,
reg->SrcRegisterInd.SwizzleX,
reg->SrcRegisterInd.SwizzleY,
reg->SrcRegisterInd.SwizzleZ,
reg->SrcRegisterInd.SwizzleW,
reg->SrcRegisterInd.Negate,
reg->SrcRegisterInd.Indirect,
reg->SrcRegisterInd.Dimension,
reg->SrcRegisterInd.Index,
reg->Indirect.File,
reg->Indirect.SwizzleX,
reg->Indirect.SwizzleY,
reg->Indirect.SwizzleZ,
reg->Indirect.SwizzleW,
reg->Indirect.Negate,
reg->Indirect.Absolute,
reg->Indirect.Indirect,
reg->Indirect.Dimension,
reg->Indirect.Index,
instruction,
header );
}
if( reg->SrcRegister.Dimension ) {
if( reg->Register.Dimension ) {
struct tgsi_dimension *dim;
assert( !reg->SrcRegisterDim.Dimension );
assert( !reg->Dimension.Dimension );
if( maxsize <= size )
return 0;
@ -713,12 +652,12 @@ tgsi_build_full_instruction(
size++;
*dim = tgsi_build_dimension(
reg->SrcRegisterDim.Indirect,
reg->SrcRegisterDim.Index,
reg->Dimension.Indirect,
reg->Dimension.Index,
instruction,
header );
if( reg->SrcRegisterDim.Indirect ) {
if( reg->Dimension.Indirect ) {
struct tgsi_src_register *ind;
if( maxsize <= size )
@ -727,15 +666,16 @@ tgsi_build_full_instruction(
size++;
*ind = tgsi_build_src_register(
reg->SrcRegisterDimInd.File,
reg->SrcRegisterDimInd.SwizzleX,
reg->SrcRegisterDimInd.SwizzleY,
reg->SrcRegisterDimInd.SwizzleZ,
reg->SrcRegisterDimInd.SwizzleW,
reg->SrcRegisterDimInd.Negate,
reg->SrcRegisterDimInd.Indirect,
reg->SrcRegisterDimInd.Dimension,
reg->SrcRegisterDimInd.Index,
reg->DimIndirect.File,
reg->DimIndirect.SwizzleX,
reg->DimIndirect.SwizzleY,
reg->DimIndirect.SwizzleZ,
reg->DimIndirect.SwizzleW,
reg->DimIndirect.Negate,
reg->DimIndirect.Absolute,
reg->DimIndirect.Indirect,
reg->DimIndirect.Dimension,
reg->DimIndirect.Index,
instruction,
header );
}
@ -786,93 +726,62 @@ tgsi_build_instruction_predicate(int index,
return instruction_predicate;
}
/** test for inequality of 32-bit values pointed to by a and b */
static INLINE boolean
compare32(const void *a, const void *b)
struct tgsi_instruction_label
tgsi_default_instruction_label( void )
{
return *((uint32_t *) a) != *((uint32_t *) b);
struct tgsi_instruction_label instruction_label;
instruction_label.Label = 0;
instruction_label.Padding = 0;
return instruction_label;
}
struct tgsi_instruction_ext_label
tgsi_default_instruction_ext_label( void )
{
struct tgsi_instruction_ext_label instruction_ext_label;
instruction_ext_label.Type = TGSI_INSTRUCTION_EXT_TYPE_LABEL;
instruction_ext_label.Label = 0;
instruction_ext_label.Padding = 0;
instruction_ext_label.Extended = 0;
return instruction_ext_label;
}
unsigned
tgsi_compare_instruction_ext_label(
struct tgsi_instruction_ext_label a,
struct tgsi_instruction_ext_label b )
{
a.Padding = b.Padding = 0;
a.Extended = b.Extended = 0;
return compare32(&a, &b);
}
struct tgsi_instruction_ext_label
tgsi_build_instruction_ext_label(
struct tgsi_instruction_label
tgsi_build_instruction_label(
unsigned label,
struct tgsi_token *prev_token,
struct tgsi_instruction *instruction,
struct tgsi_header *header )
{
struct tgsi_instruction_ext_label instruction_ext_label;
struct tgsi_instruction_label instruction_label;
instruction_ext_label = tgsi_default_instruction_ext_label();
instruction_ext_label.Label = label;
instruction_label = tgsi_default_instruction_label();
instruction_label.Label = label;
instruction->Label = 1;
prev_token->Extended = 1;
instruction_grow( instruction, header );
return instruction_ext_label;
return instruction_label;
}
struct tgsi_instruction_ext_texture
tgsi_default_instruction_ext_texture( void )
struct tgsi_instruction_texture
tgsi_default_instruction_texture( void )
{
struct tgsi_instruction_ext_texture instruction_ext_texture;
struct tgsi_instruction_texture instruction_texture;
instruction_ext_texture.Type = TGSI_INSTRUCTION_EXT_TYPE_TEXTURE;
instruction_ext_texture.Texture = TGSI_TEXTURE_UNKNOWN;
instruction_ext_texture.Padding = 0;
instruction_ext_texture.Extended = 0;
instruction_texture.Texture = TGSI_TEXTURE_UNKNOWN;
instruction_texture.Padding = 0;
return instruction_ext_texture;
return instruction_texture;
}
unsigned
tgsi_compare_instruction_ext_texture(
struct tgsi_instruction_ext_texture a,
struct tgsi_instruction_ext_texture b )
{
a.Padding = b.Padding = 0;
a.Extended = b.Extended = 0;
return compare32(&a, &b);
}
struct tgsi_instruction_ext_texture
tgsi_build_instruction_ext_texture(
struct tgsi_instruction_texture
tgsi_build_instruction_texture(
unsigned texture,
struct tgsi_token *prev_token,
struct tgsi_instruction *instruction,
struct tgsi_header *header )
{
struct tgsi_instruction_ext_texture instruction_ext_texture;
struct tgsi_instruction_texture instruction_texture;
instruction_ext_texture = tgsi_default_instruction_ext_texture();
instruction_ext_texture.Texture = texture;
instruction_texture = tgsi_default_instruction_texture();
instruction_texture.Texture = texture;
instruction->Texture = 1;
prev_token->Extended = 1;
instruction_grow( instruction, header );
return instruction_ext_texture;
return instruction_texture;
}
struct tgsi_src_register
@ -886,10 +795,10 @@ tgsi_default_src_register( void )
src_register.SwizzleZ = TGSI_SWIZZLE_Z;
src_register.SwizzleW = TGSI_SWIZZLE_W;
src_register.Negate = 0;
src_register.Absolute = 0;
src_register.Indirect = 0;
src_register.Dimension = 0;
src_register.Index = 0;
src_register.Extended = 0;
return src_register;
}
@ -902,6 +811,7 @@ tgsi_build_src_register(
unsigned swizzle_z,
unsigned swizzle_w,
unsigned negate,
unsigned absolute,
unsigned indirect,
unsigned dimension,
int index,
@ -925,6 +835,7 @@ tgsi_build_src_register(
src_register.SwizzleZ = swizzle_z;
src_register.SwizzleW = swizzle_w;
src_register.Negate = negate;
src_register.Absolute = absolute;
src_register.Indirect = indirect;
src_register.Dimension = dimension;
src_register.Index = index;
@ -939,75 +850,15 @@ tgsi_default_full_src_register( void )
{
struct tgsi_full_src_register full_src_register;
full_src_register.SrcRegister = tgsi_default_src_register();
full_src_register.SrcRegisterExtMod = tgsi_default_src_register_ext_mod();
full_src_register.SrcRegisterInd = tgsi_default_src_register();
full_src_register.SrcRegisterDim = tgsi_default_dimension();
full_src_register.SrcRegisterDimInd = tgsi_default_src_register();
full_src_register.Register = tgsi_default_src_register();
full_src_register.Indirect = tgsi_default_src_register();
full_src_register.Dimension = tgsi_default_dimension();
full_src_register.DimIndirect = tgsi_default_src_register();
return full_src_register;
}
struct tgsi_src_register_ext_mod
tgsi_default_src_register_ext_mod( void )
{
struct tgsi_src_register_ext_mod src_register_ext_mod;
src_register_ext_mod.Type = TGSI_SRC_REGISTER_EXT_TYPE_MOD;
src_register_ext_mod.Complement = 0;
src_register_ext_mod.Bias = 0;
src_register_ext_mod.Scale2X = 0;
src_register_ext_mod.Absolute = 0;
src_register_ext_mod.Negate = 0;
src_register_ext_mod.Padding = 0;
src_register_ext_mod.Extended = 0;
return src_register_ext_mod;
}
unsigned
tgsi_compare_src_register_ext_mod(
struct tgsi_src_register_ext_mod a,
struct tgsi_src_register_ext_mod b )
{
a.Padding = b.Padding = 0;
a.Extended = b.Extended = 0;
return compare32(&a, &b);
}
struct tgsi_src_register_ext_mod
tgsi_build_src_register_ext_mod(
unsigned complement,
unsigned bias,
unsigned scale_2x,
unsigned absolute,
unsigned negate,
struct tgsi_token *prev_token,
struct tgsi_instruction *instruction,
struct tgsi_header *header )
{
struct tgsi_src_register_ext_mod src_register_ext_mod;
assert( complement <= 1 );
assert( bias <= 1 );
assert( scale_2x <= 1 );
assert( absolute <= 1 );
assert( negate <= 1 );
src_register_ext_mod = tgsi_default_src_register_ext_mod();
src_register_ext_mod.Complement = complement;
src_register_ext_mod.Bias = bias;
src_register_ext_mod.Scale2X = scale_2x;
src_register_ext_mod.Absolute = absolute;
src_register_ext_mod.Negate = negate;
prev_token->Extended = 1;
instruction_grow( instruction, header );
return src_register_ext_mod;
}
struct tgsi_dimension
tgsi_default_dimension( void )
{
@ -1017,7 +868,6 @@ tgsi_default_dimension( void )
dimension.Dimension = 0;
dimension.Padding = 0;
dimension.Index = 0;
dimension.Extended = 0;
return dimension;
}
@ -1051,7 +901,6 @@ tgsi_default_dst_register( void )
dst_register.Dimension = 0;
dst_register.Index = 0;
dst_register.Padding = 0;
dst_register.Extended = 0;
return dst_register;
}
@ -1087,53 +936,9 @@ tgsi_default_full_dst_register( void )
{
struct tgsi_full_dst_register full_dst_register;
full_dst_register.DstRegister = tgsi_default_dst_register();
full_dst_register.DstRegisterInd = tgsi_default_src_register();
full_dst_register.DstRegisterExtModulate =
tgsi_default_dst_register_ext_modulate();
full_dst_register.Register = tgsi_default_dst_register();
full_dst_register.Indirect = tgsi_default_src_register();
return full_dst_register;
}
struct tgsi_dst_register_ext_modulate
tgsi_default_dst_register_ext_modulate( void )
{
struct tgsi_dst_register_ext_modulate dst_register_ext_modulate;
dst_register_ext_modulate.Type = TGSI_DST_REGISTER_EXT_TYPE_MODULATE;
dst_register_ext_modulate.Modulate = TGSI_MODULATE_1X;
dst_register_ext_modulate.Padding = 0;
dst_register_ext_modulate.Extended = 0;
return dst_register_ext_modulate;
}
unsigned
tgsi_compare_dst_register_ext_modulate(
struct tgsi_dst_register_ext_modulate a,
struct tgsi_dst_register_ext_modulate b )
{
a.Padding = b.Padding = 0;
a.Extended = b.Extended = 0;
return compare32(&a, &b);
}
struct tgsi_dst_register_ext_modulate
tgsi_build_dst_register_ext_modulate(
unsigned modulate,
struct tgsi_token *prev_token,
struct tgsi_instruction *instruction,
struct tgsi_header *header )
{
struct tgsi_dst_register_ext_modulate dst_register_ext_modulate;
assert( modulate <= TGSI_MODULATE_EIGHTH );
dst_register_ext_modulate = tgsi_default_dst_register_ext_modulate();
dst_register_ext_modulate.Modulate = modulate;
prev_token->Extended = 1;
instruction_grow( instruction, header );
return dst_register_ext_modulate;
}

65
src/gallium/auxiliary/tgsi/tgsi_build.h
View file

@ -36,12 +36,6 @@ struct tgsi_token;
extern "C" {
#endif
/*
* version
*/
struct tgsi_version
tgsi_build_version( void );
/*
* header
@ -171,31 +165,21 @@ tgsi_build_instruction_predicate(int index,
struct tgsi_instruction *instruction,
struct tgsi_header *header);
struct tgsi_instruction_ext_label
tgsi_default_instruction_ext_label( void );
struct tgsi_instruction_label
tgsi_default_instruction_label( void );
unsigned
tgsi_compare_instruction_ext_label(
struct tgsi_instruction_ext_label a,
struct tgsi_instruction_ext_label b );
struct tgsi_instruction_ext_label
tgsi_build_instruction_ext_label(
struct tgsi_instruction_label
tgsi_build_instruction_label(
unsigned label,
struct tgsi_token *prev_token,
struct tgsi_instruction *instruction,
struct tgsi_header *header );
struct tgsi_instruction_ext_texture
tgsi_default_instruction_ext_texture( void );
struct tgsi_instruction_texture
tgsi_default_instruction_texture( void );
unsigned
tgsi_compare_instruction_ext_texture(
struct tgsi_instruction_ext_texture a,
struct tgsi_instruction_ext_texture b );
struct tgsi_instruction_ext_texture
tgsi_build_instruction_ext_texture(
struct tgsi_instruction_texture
tgsi_build_instruction_texture(
unsigned texture,
struct tgsi_token *prev_token,
struct tgsi_instruction *instruction,
@ -212,6 +196,7 @@ tgsi_build_src_register(
unsigned swizzle_z,
unsigned swizzle_w,
unsigned negate,
unsigned absolute,
unsigned indirect,
unsigned dimension,
int index,
@ -221,24 +206,6 @@ tgsi_build_src_register(
struct tgsi_full_src_register
tgsi_default_full_src_register( void );
struct tgsi_src_register_ext_mod
tgsi_default_src_register_ext_mod( void );
unsigned
tgsi_compare_src_register_ext_mod(
struct tgsi_src_register_ext_mod a,
struct tgsi_src_register_ext_mod b );
struct tgsi_src_register_ext_mod
tgsi_build_src_register_ext_mod(
unsigned complement,
unsigned bias,
unsigned scale_2x,
unsigned absolute,
unsigned negate,
struct tgsi_token *prev_token,
struct tgsi_instruction *instruction,
struct tgsi_header *header );
struct tgsi_dimension
tgsi_default_dimension( void );
@ -265,20 +232,6 @@ tgsi_build_dst_register(
struct tgsi_full_dst_register
tgsi_default_full_dst_register( void );
struct tgsi_dst_register_ext_modulate
tgsi_default_dst_register_ext_modulate( void );
unsigned
tgsi_compare_dst_register_ext_modulate(
struct tgsi_dst_register_ext_modulate a,
struct tgsi_dst_register_ext_modulate b );
struct tgsi_dst_register_ext_modulate
tgsi_build_dst_register_ext_modulate(
unsigned modulate,
struct tgsi_token *prev_token,
struct tgsi_instruction *instruction,
struct tgsi_header *header );
#if defined __cplusplus
}

113
src/gallium/auxiliary/tgsi/tgsi_dump.c
View file

@ -150,17 +150,6 @@ static const char *texture_names[] =
};
static const char *modulate_names[TGSI_MODULATE_COUNT] =
{
"",
"_2X",
"_4X",
"_8X",
"_D2",
"_D4",
"_D8"
};
static void
_dump_register(
struct dump_ctx *ctx,
@ -235,19 +224,19 @@ iter_declaration(
_dump_register(
ctx,
decl->Declaration.File,
decl->DeclarationRange.First,
decl->DeclarationRange.Last );
decl->Range.First,
decl->Range.Last );
_dump_writemask(
ctx,
decl->Declaration.UsageMask );
if (decl->Declaration.Semantic) {
TXT( ", " );
ENM( decl->Semantic.SemanticName, semantic_names );
if (decl->Semantic.SemanticIndex != 0 ||
decl->Semantic.SemanticName == TGSI_SEMANTIC_GENERIC) {
ENM( decl->Semantic.Name, semantic_names );
if (decl->Semantic.Index != 0 ||
decl->Semantic.Name == TGSI_SEMANTIC_GENERIC) {
CHR( '[' );
UID( decl->Semantic.SemanticIndex );
UID( decl->Semantic.Index );
CHR( ']' );
}
}
@ -363,99 +352,84 @@ iter_instruction(
}
for (i = 0; i < inst->Instruction.NumDstRegs; i++) {
const struct tgsi_full_dst_register *dst = &inst->FullDstRegisters[i];
const struct tgsi_full_dst_register *dst = &inst->Dst[i];
if (!first_reg)
CHR( ',' );
CHR( ' ' );
if (dst->DstRegister.Indirect) {
if (dst->Register.Indirect) {
_dump_register_ind(
ctx,
dst->DstRegister.File,
dst->DstRegister.Index,
dst->DstRegisterInd.File,
dst->DstRegisterInd.Index,
dst->DstRegisterInd.SwizzleX );
dst->Register.File,
dst->Register.Index,
dst->Indirect.File,
dst->Indirect.Index,
dst->Indirect.SwizzleX );
}
else {
_dump_register(
ctx,
dst->DstRegister.File,
dst->DstRegister.Index,
dst->DstRegister.Index );
dst->Register.File,
dst->Register.Index,
dst->Register.Index );
}
ENM( dst->DstRegisterExtModulate.Modulate, modulate_names );
_dump_writemask( ctx, dst->DstRegister.WriteMask );
_dump_writemask( ctx, dst->Register.WriteMask );
first_reg = FALSE;
}
for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
const struct tgsi_full_src_register *src = &inst->FullSrcRegisters[i];
const struct tgsi_full_src_register *src = &inst->Src[i];
if (!first_reg)
CHR( ',' );
CHR( ' ' );
if (src->SrcRegisterExtMod.Negate)
if (src->Register.Negate)
TXT( "-(" );
if (src->SrcRegisterExtMod.Absolute)
if (src->Register.Absolute)
CHR( '|' );
if (src->SrcRegisterExtMod.Scale2X)
TXT( "2*(" );
if (src->SrcRegisterExtMod.Bias)
CHR( '(' );
if (src->SrcRegisterExtMod.Complement)
TXT( "1-(" );
if (src->SrcRegister.Negate)
CHR( '-' );
if (src->SrcRegister.Indirect) {
if (src->Register.Indirect) {
_dump_register_ind(
ctx,
src->SrcRegister.File,
src->SrcRegister.Index,
src->SrcRegisterInd.File,
src->SrcRegisterInd.Index,
src->SrcRegisterInd.SwizzleX );
src->Register.File,
src->Register.Index,
src->Indirect.File,
src->Indirect.Index,
src->Indirect.SwizzleX );
}
else {
_dump_register(
ctx,
src->SrcRegister.File,
src->SrcRegister.Index,
src->SrcRegister.Index );
src->Register.File,
src->Register.Index,
src->Register.Index );
}
if (src->SrcRegister.SwizzleX != TGSI_SWIZZLE_X ||
src->SrcRegister.SwizzleY != TGSI_SWIZZLE_Y ||
src->SrcRegister.SwizzleZ != TGSI_SWIZZLE_Z ||
src->SrcRegister.SwizzleW != TGSI_SWIZZLE_W) {
if (src->Register.SwizzleX != TGSI_SWIZZLE_X ||
src->Register.SwizzleY != TGSI_SWIZZLE_Y ||
src->Register.SwizzleZ != TGSI_SWIZZLE_Z ||
src->Register.SwizzleW != TGSI_SWIZZLE_W) {
CHR( '.' );
ENM( src->SrcRegister.SwizzleX, swizzle_names );
ENM( src->SrcRegister.SwizzleY, swizzle_names );
ENM( src->SrcRegister.SwizzleZ, swizzle_names );
ENM( src->SrcRegister.SwizzleW, swizzle_names );
ENM( src->Register.SwizzleX, swizzle_names );
ENM( src->Register.SwizzleY, swizzle_names );
ENM( src->Register.SwizzleZ, swizzle_names );
ENM( src->Register.SwizzleW, swizzle_names );
}
if (src->SrcRegisterExtMod.Complement)
CHR( ')' );
if (src->SrcRegisterExtMod.Bias)
TXT( ")-.5" );
if (src->SrcRegisterExtMod.Scale2X)
CHR( ')' );
if (src->SrcRegisterExtMod.Absolute)
if (src->Register.Absolute)
CHR( '|' );
if (src->SrcRegisterExtMod.Negate)
if (src->Register.Negate)
CHR( ')' );
first_reg = FALSE;
}
if (inst->InstructionExtTexture.Texture != TGSI_TEXTURE_UNKNOWN) {
if (inst->Instruction.Texture) {
TXT( ", " );
ENM( inst->InstructionExtTexture.Texture, texture_names );
ENM( inst->Texture.Texture, texture_names );
}
switch (inst->Instruction.Opcode) {
@ -465,7 +439,7 @@ iter_instruction(
case TGSI_OPCODE_ENDLOOP:
case TGSI_OPCODE_CAL:
TXT( " :" );
UID( inst->InstructionExtLabel.Label );
UID( inst->Label.Label );
break;
}
@ -503,9 +477,6 @@ prolog(
{
struct dump_ctx *ctx = (struct dump_ctx *) iter;
ENM( iter->processor.Processor, processor_type_names );
UID( iter->version.MajorVersion );
CHR( '.' );
UID( iter->version.MinorVersion );
EOL();
return TRUE;
}

228
src/gallium/auxiliary/tgsi/tgsi_dump_c.c
View file

@ -113,13 +113,6 @@ static const char *TGSI_SATS[] =
"SAT_MINUS_PLUS_ONE"
};
static const char *TGSI_INSTRUCTION_EXTS[] =
{
"",
"INSTRUCTION_EXT_TYPE_LABEL",
"INSTRUCTION_EXT_TYPE_TEXTURE"
};
static const char *TGSI_SWIZZLES[] =
{
"SWIZZLE_X",
@ -141,12 +134,6 @@ static const char *TGSI_TEXTURES[] =
"TEXTURE_SHADOWRECT"
};
static const char *TGSI_SRC_REGISTER_EXTS[] =
{
"",
"SRC_REGISTER_EXT_TYPE_MOD"
};
static const char *TGSI_WRITEMASKS[] =
{
"0",
@ -167,23 +154,6 @@ static const char *TGSI_WRITEMASKS[] =
"WRITEMASK_XYZW"
};
static const char *TGSI_DST_REGISTER_EXTS[] =
{
"",
"DST_REGISTER_EXT_TYPE_MODULATE"
};
static const char *TGSI_MODULATES[] =
{
"MODULATE_1X",
"MODULATE_2X",
"MODULATE_4X",
"MODULATE_8X",
"MODULATE_HALF",
"MODULATE_QUARTER",
"MODULATE_EIGHTH"
};
static void
dump_declaration_verbose(
struct tgsi_full_declaration *decl,
@ -216,6 +186,14 @@ dump_declaration_verbose(
TXT( "\nSemantic : " );
UID( decl->Declaration.Semantic );
}
if (deflt || fd->Declaration.Centroid != decl->Declaration.Centroid) {
TXT("\nCentroid : ");
UID(decl->Declaration.Centroid);
}
if (deflt || fd->Declaration.Invariant != decl->Declaration.Invariant) {
TXT("\nInvariant : ");
UID(decl->Declaration.Invariant);
}
if( ignored ) {
TXT( "\nPadding : " );
UIX( decl->Declaration.Padding );
@ -223,16 +201,16 @@ dump_declaration_verbose(
EOL();
TXT( "\nFirst: " );
UID( decl->DeclarationRange.First );
UID( decl->Range.First );
TXT( "\nLast : " );
UID( decl->DeclarationRange.Last );
UID( decl->Range.Last );
if( decl->Declaration.Semantic ) {
EOL();
TXT( "\nSemanticName : " );
ENM( decl->Semantic.SemanticName, TGSI_SEMANTICS );
TXT( "\nSemanticIndex: " );
UID( decl->Semantic.SemanticIndex );
TXT( "\nName : " );
ENM( decl->Semantic.Name, TGSI_SEMANTICS );
TXT( "\nIndex: " );
UID( decl->Semantic.Index );
if( ignored ) {
TXT( "\nPadding : " );
UIX( decl->Semantic.Padding );
@ -292,180 +270,122 @@ dump_instruction_verbose(
TXT( "\nNumSrcRegs : " );
UID( inst->Instruction.NumSrcRegs );
}
if (deflt || fi->Instruction.Predicate != inst->Instruction.Predicate) {
TXT("\nPredicate : ");
UID(inst->Instruction.Predicate);
}
if (deflt || fi->Instruction.Label != inst->Instruction.Label) {
TXT("\nLabel : ");
UID(inst->Instruction.Label);
}
if (deflt || fi->Instruction.Texture != inst->Instruction.Texture) {
TXT("\nTexture : ");
UID(inst->Instruction.Texture);
}
if( ignored ) {
TXT( "\nPadding : " );
UIX( inst->Instruction.Padding );
}
if( deflt || tgsi_compare_instruction_ext_label( inst->InstructionExtLabel, fi->InstructionExtLabel ) ) {
if (deflt || inst->Instruction.Label) {
EOL();
TXT( "\nType : " );
ENM( inst->InstructionExtLabel.Type, TGSI_INSTRUCTION_EXTS );
if( deflt || fi->InstructionExtLabel.Label != inst->InstructionExtLabel.Label ) {
if (deflt || fi->Label.Label != inst->Label.Label) {
TXT( "\nLabel : " );
UID( inst->InstructionExtLabel.Label );
UID(inst->Label.Label);
}
if( ignored ) {
TXT( "\nPadding : " );
UIX( inst->InstructionExtLabel.Padding );
if( deflt || fi->InstructionExtLabel.Extended != inst->InstructionExtLabel.Extended ) {
TXT( "\nExtended: " );
UID( inst->InstructionExtLabel.Extended );
}
UIX(inst->Label.Padding);
}
}
if( deflt || tgsi_compare_instruction_ext_texture( inst->InstructionExtTexture, fi->InstructionExtTexture ) ) {
if (deflt || inst->Instruction.Texture) {
EOL();
TXT( "\nType : " );
ENM( inst->InstructionExtTexture.Type, TGSI_INSTRUCTION_EXTS );
if( deflt || fi->InstructionExtTexture.Texture != inst->InstructionExtTexture.Texture ) {
if (deflt || fi->Texture.Texture != inst->Texture.Texture) {
TXT( "\nTexture : " );
ENM( inst->InstructionExtTexture.Texture, TGSI_TEXTURES );
ENM(inst->Texture.Texture, TGSI_TEXTURES);
}
if( ignored ) {
TXT( "\nPadding : " );
UIX( inst->InstructionExtTexture.Padding );
if( deflt || fi->InstructionExtTexture.Extended != inst->InstructionExtTexture.Extended ) {
TXT( "\nExtended: " );
UID( inst->InstructionExtTexture.Extended );
}
UIX(inst->Texture.Padding);
}
}
for( i = 0; i < inst->Instruction.NumDstRegs; i++ ) {
struct tgsi_full_dst_register *dst = &inst->FullDstRegisters[i];
struct tgsi_full_dst_register *fd = &fi->FullDstRegisters[i];
struct tgsi_full_dst_register *dst = &inst->Dst[i];
struct tgsi_full_dst_register *fd = &fi->Dst[i];
EOL();
TXT( "\nFile : " );
ENM( dst->DstRegister.File, TGSI_FILES );
if( deflt || fd->DstRegister.WriteMask != dst->DstRegister.WriteMask ) {
ENM( dst->Register.File, TGSI_FILES );
if( deflt || fd->Register.WriteMask != dst->Register.WriteMask ) {
TXT( "\nWriteMask: " );
ENM( dst->DstRegister.WriteMask, TGSI_WRITEMASKS );
ENM( dst->Register.WriteMask, TGSI_WRITEMASKS );
}
if( ignored ) {
if( deflt || fd->DstRegister.Indirect != dst->DstRegister.Indirect ) {
if( deflt || fd->Register.Indirect != dst->Register.Indirect ) {
TXT( "\nIndirect : " );
UID( dst->DstRegister.Indirect );
UID( dst->Register.Indirect );
}
if( deflt || fd->DstRegister.Dimension != dst->DstRegister.Dimension ) {
if( deflt || fd->Register.Dimension != dst->Register.Dimension ) {
TXT( "\nDimension: " );
UID( dst->DstRegister.Dimension );
UID( dst->Register.Dimension );
}
}
if( deflt || fd->DstRegister.Index != dst->DstRegister.Index ) {
if( deflt || fd->Register.Index != dst->Register.Index ) {
TXT( "\nIndex : " );
SID( dst->DstRegister.Index );
SID( dst->Register.Index );
}
if( ignored ) {
TXT( "\nPadding : " );
UIX( dst->DstRegister.Padding );
if( deflt || fd->DstRegister.Extended != dst->DstRegister.Extended ) {
TXT( "\nExtended : " );
UID( dst->DstRegister.Extended );
}
}
if( deflt || tgsi_compare_dst_register_ext_modulate( dst->DstRegisterExtModulate, fd->DstRegisterExtModulate ) ) {
EOL();
TXT( "\nType : " );
ENM( dst->DstRegisterExtModulate.Type, TGSI_DST_REGISTER_EXTS );
if( deflt || fd->DstRegisterExtModulate.Modulate != dst->DstRegisterExtModulate.Modulate ) {
TXT( "\nModulate: " );
ENM( dst->DstRegisterExtModulate.Modulate, TGSI_MODULATES );
}
if( ignored ) {
TXT( "\nPadding : " );
UIX( dst->DstRegisterExtModulate.Padding );
if( deflt || fd->DstRegisterExtModulate.Extended != dst->DstRegisterExtModulate.Extended ) {
TXT( "\nExtended: " );
UID( dst->DstRegisterExtModulate.Extended );
}
}
UIX( dst->Register.Padding );
}
}
for( i = 0; i < inst->Instruction.NumSrcRegs; i++ ) {
struct tgsi_full_src_register *src = &inst->FullSrcRegisters[i];
struct tgsi_full_src_register *fs = &fi->FullSrcRegisters[i];
struct tgsi_full_src_register *src = &inst->Src[i];
struct tgsi_full_src_register *fs = &fi->Src[i];
EOL();
TXT( "\nFile : ");
ENM( src->SrcRegister.File, TGSI_FILES );
if( deflt || fs->SrcRegister.SwizzleX != src->SrcRegister.SwizzleX ) {
ENM( src->Register.File, TGSI_FILES );
if( deflt || fs->Register.SwizzleX != src->Register.SwizzleX ) {
TXT( "\nSwizzleX : " );
ENM( src->SrcRegister.SwizzleX, TGSI_SWIZZLES );
ENM( src->Register.SwizzleX, TGSI_SWIZZLES );
}
if( deflt || fs->SrcRegister.SwizzleY != src->SrcRegister.SwizzleY ) {
if( deflt || fs->Register.SwizzleY != src->Register.SwizzleY ) {
TXT( "\nSwizzleY : " );
ENM( src->SrcRegister.SwizzleY, TGSI_SWIZZLES );
ENM( src->Register.SwizzleY, TGSI_SWIZZLES );
}
if( deflt || fs->SrcRegister.SwizzleZ != src->SrcRegister.SwizzleZ ) {
if( deflt || fs->Register.SwizzleZ != src->Register.SwizzleZ ) {
TXT( "\nSwizzleZ : " );
ENM( src->SrcRegister.SwizzleZ, TGSI_SWIZZLES );
ENM( src->Register.SwizzleZ, TGSI_SWIZZLES );
}
if( deflt || fs->SrcRegister.SwizzleW != src->SrcRegister.SwizzleW ) {
if( deflt || fs->Register.SwizzleW != src->Register.SwizzleW ) {
TXT( "\nSwizzleW : " );
ENM( src->SrcRegister.SwizzleW, TGSI_SWIZZLES );
ENM( src->Register.SwizzleW, TGSI_SWIZZLES );
}
if( deflt || fs->SrcRegister.Negate != src->SrcRegister.Negate ) {
if (deflt || fs->Register.Absolute != src->Register.Absolute) {
TXT("\nAbsolute : ");
UID(src->Register.Absolute);
}
if( deflt || fs->Register.Negate != src->Register.Negate ) {
TXT( "\nNegate : " );
UID( src->SrcRegister.Negate );
UID( src->Register.Negate );
}
if( ignored ) {
if( deflt || fs->SrcRegister.Indirect != src->SrcRegister.Indirect ) {
if( deflt || fs->Register.Indirect != src->Register.Indirect ) {
TXT( "\nIndirect : " );
UID( src->SrcRegister.Indirect );
UID( src->Register.Indirect );
}
if( deflt || fs->SrcRegister.Dimension != src->SrcRegister.Dimension ) {
if( deflt || fs->Register.Dimension != src->Register.Dimension ) {
TXT( "\nDimension: " );
UID( src->SrcRegister.Dimension );
UID( src->Register.Dimension );
}
}
if( deflt || fs->SrcRegister.Index != src->SrcRegister.Index ) {
if( deflt || fs->Register.Index != src->Register.Index ) {
TXT( "\nIndex : " );
SID( src->SrcRegister.Index );
}
if( ignored ) {
if( deflt || fs->SrcRegister.Extended != src->SrcRegister.Extended ) {
TXT( "\nExtended : " );
UID( src->SrcRegister.Extended );
}
}
if( deflt || tgsi_compare_src_register_ext_mod( src->SrcRegisterExtMod, fs->SrcRegisterExtMod ) ) {
EOL();
TXT( "\nType : " );
ENM( src->SrcRegisterExtMod.Type, TGSI_SRC_REGISTER_EXTS );
if( deflt || fs->SrcRegisterExtMod.Complement != src->SrcRegisterExtMod.Complement ) {
TXT( "\nComplement: " );
UID( src->SrcRegisterExtMod.Complement );
}
if( deflt || fs->SrcRegisterExtMod.Bias != src->SrcRegisterExtMod.Bias ) {
TXT( "\nBias : " );
UID( src->SrcRegisterExtMod.Bias );
}
if( deflt || fs->SrcRegisterExtMod.Scale2X != src->SrcRegisterExtMod.Scale2X ) {
TXT( "\nScale2X : " );
UID( src->SrcRegisterExtMod.Scale2X );
}
if( deflt || fs->SrcRegisterExtMod.Absolute != src->SrcRegisterExtMod.Absolute ) {
TXT( "\nAbsolute : " );
UID( src->SrcRegisterExtMod.Absolute );
}
if( deflt || fs->SrcRegisterExtMod.Negate != src->SrcRegisterExtMod.Negate ) {
TXT( "\nNegate : " );
UID( src->SrcRegisterExtMod.Negate );
}
if( ignored ) {
TXT( "\nPadding : " );
UIX( src->SrcRegisterExtMod.Padding );
if( deflt || fs->SrcRegisterExtMod.Extended != src->SrcRegisterExtMod.Extended ) {
TXT( "\nExtended : " );
UID( src->SrcRegisterExtMod.Extended );
}
}
SID( src->Register.Index );
}
}
}
@ -485,12 +405,6 @@ tgsi_dump_c(
TXT( "tgsi-dump begin -----------------" );
TXT( "\nMajorVersion: " );
UID( parse.FullVersion.Version.MajorVersion );
TXT( "\nMinorVersion: " );
UID( parse.FullVersion.Version.MinorVersion );
EOL();
TXT( "\nHeaderSize: " );
UID( parse.FullHeader.Header.HeaderSize );
TXT( "\nBodySize : " );
@ -510,10 +424,6 @@ tgsi_dump_c(
if( ignored ) {
TXT( "\nSize : " );
UID( parse.FullToken.Token.NrTokens );
if( deflt || parse.FullToken.Token.Extended ) {
TXT( "\nExtended : " );
UID( parse.FullToken.Token.Extended );
}
}
switch( parse.FullToken.Token.Type ) {

140
src/gallium/auxiliary/tgsi/tgsi_exec.c
View file

@ -107,10 +107,10 @@
#define TEMP_P0 TGSI_EXEC_TEMP_P0
#define IS_CHANNEL_ENABLED(INST, CHAN)\
((INST).FullDstRegisters[0].DstRegister.WriteMask & (1 << (CHAN)))
((INST).Dst[0].Register.WriteMask & (1 << (CHAN)))
#define IS_CHANNEL_ENABLED2(INST, CHAN)\
((INST).FullDstRegisters[1].DstRegister.WriteMask & (1 << (CHAN)))
((INST).Dst[1].Register.WriteMask & (1 << (CHAN)))
#define FOR_EACH_ENABLED_CHANNEL(INST, CHAN)\
for (CHAN = 0; CHAN < NUM_CHANNELS; CHAN++)\
@ -188,7 +188,7 @@ tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst)
{
uint i, chan;
uint writemask = inst->FullDstRegisters[0].DstRegister.WriteMask;
uint writemask = inst->Dst[0].Register.WriteMask;
if (writemask == TGSI_WRITEMASK_X ||
writemask == TGSI_WRITEMASK_Y ||
writemask == TGSI_WRITEMASK_Z ||
@ -200,15 +200,15 @@ tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst)
/* loop over src regs */
for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
if ((inst->FullSrcRegisters[i].SrcRegister.File ==
inst->FullDstRegisters[0].DstRegister.File) &&
(inst->FullSrcRegisters[i].SrcRegister.Index ==
inst->FullDstRegisters[0].DstRegister.Index)) {
if ((inst->Src[i].Register.File ==
inst->Dst[0].Register.File) &&
(inst->Src[i].Register.Index ==
inst->Dst[0].Register.Index)) {
/* loop over dest channels */
uint channelsWritten = 0x0;
FOR_EACH_ENABLED_CHANNEL(*inst, chan) {
/* check if we're reading a channel that's been written */
uint swizzle = tgsi_util_get_full_src_register_swizzle(&inst->FullSrcRegisters[i], chan);
uint swizzle = tgsi_util_get_full_src_register_swizzle(&inst->Src[i], chan);
if (channelsWritten & (1 << swizzle)) {
return TRUE;
}
@ -1233,13 +1233,13 @@ fetch_source(
*
* file[1],
* where:
* file = SrcRegister.File
* [1] = SrcRegister.Index
* file = Register.File
* [1] = Register.Index
*/
index.i[0] =
index.i[1] =
index.i[2] =
index.i[3] = reg->SrcRegister.Index;
index.i[3] = reg->Register.Index;
/* There is an extra source register that indirectly subscripts
* a register file. The direct index now becomes an offset
@ -1247,11 +1247,11 @@ fetch_source(
*
* file[ind[2].x+1],
* where:
* ind = SrcRegisterInd.File
* [2] = SrcRegisterInd.Index
* .x = SrcRegisterInd.SwizzleX
* ind = Indirect.File
* [2] = Indirect.Index
* .x = Indirect.SwizzleX
*/
if (reg->SrcRegister.Indirect) {
if (reg->Register.Indirect) {
union tgsi_exec_channel index2;
union tgsi_exec_channel indir_index;
const uint execmask = mach->ExecMask;
@ -1261,13 +1261,13 @@ fetch_source(
index2.i[0] =
index2.i[1] =
index2.i[2] =
index2.i[3] = reg->SrcRegisterInd.Index;
index2.i[3] = reg->Indirect.Index;
/* get current value of address register[swizzle] */
swizzle = tgsi_util_get_src_register_swizzle( &reg->SrcRegisterInd, CHAN_X );
swizzle = tgsi_util_get_src_register_swizzle( &reg->Indirect, CHAN_X );
fetch_src_file_channel(
mach,
reg->SrcRegisterInd.File,
reg->Indirect.File,
swizzle,
&index2,
&indir_index );
@ -1293,14 +1293,14 @@ fetch_source(
*
* file[1][3] == file[1*sizeof(file[1])+3],
* where:
* [3] = SrcRegisterDim.Index
* [3] = Dimension.Index
*/
if (reg->SrcRegister.Dimension) {
if (reg->Register.Dimension) {
/* The size of the first-order array depends on the register file type.
* We need to multiply the index to the first array to get an effective,
* "flat" index that points to the beginning of the second-order array.
*/
switch (reg->SrcRegister.File) {
switch (reg->Register.File) {
case TGSI_FILE_INPUT:
index.i[0] *= TGSI_EXEC_MAX_INPUT_ATTRIBS;
index.i[1] *= TGSI_EXEC_MAX_INPUT_ATTRIBS;
@ -1317,10 +1317,10 @@ fetch_source(
assert( 0 );
}
index.i[0] += reg->SrcRegisterDim.Index;
index.i[1] += reg->SrcRegisterDim.Index;
index.i[2] += reg->SrcRegisterDim.Index;
index.i[3] += reg->SrcRegisterDim.Index;
index.i[0] += reg->Dimension.Index;
index.i[1] += reg->Dimension.Index;
index.i[2] += reg->Dimension.Index;
index.i[3] += reg->Dimension.Index;
/* Again, the second subscript index can be addressed indirectly
* identically to the first one.
@ -1329,11 +1329,11 @@ fetch_source(
*
* file[1][ind[4].y+3],
* where:
* ind = SrcRegisterDimInd.File
* [4] = SrcRegisterDimInd.Index
* .y = SrcRegisterDimInd.SwizzleX
* ind = DimIndirect.File
* [4] = DimIndirect.Index
* .y = DimIndirect.SwizzleX
*/
if (reg->SrcRegisterDim.Indirect) {
if (reg->Dimension.Indirect) {
union tgsi_exec_channel index2;
union tgsi_exec_channel indir_index;
const uint execmask = mach->ExecMask;
@ -1342,12 +1342,12 @@ fetch_source(
index2.i[0] =
index2.i[1] =
index2.i[2] =
index2.i[3] = reg->SrcRegisterDimInd.Index;
index2.i[3] = reg->DimIndirect.Index;
swizzle = tgsi_util_get_src_register_swizzle( &reg->SrcRegisterDimInd, CHAN_X );
swizzle = tgsi_util_get_src_register_swizzle( &reg->DimIndirect, CHAN_X );
fetch_src_file_channel(
mach,
reg->SrcRegisterDimInd.File,
reg->DimIndirect.File,
swizzle,
&index2,
&indir_index );
@ -1367,7 +1367,7 @@ fetch_source(
}
/* If by any chance there was a need for a 3D array of register
* files, we would have to check whether SrcRegisterDim is followed
* files, we would have to check whether Dimension is followed
* by a dimension register and continue the saga.
*/
}
@ -1375,7 +1375,7 @@ fetch_source(
swizzle = tgsi_util_get_full_src_register_swizzle( reg, chan_index );
fetch_src_file_channel(
mach,
reg->SrcRegister.File,
reg->Register.File,
swizzle,
&index,
chan );
@ -1397,10 +1397,6 @@ fetch_source(
case TGSI_UTIL_SIGN_KEEP:
break;
}
if (reg->SrcRegisterExtMod.Complement) {
micro_sub( chan, &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], chan );
}
}
static void
@ -1428,11 +1424,11 @@ store_dest(
*
* file[ind[2].x+1],
* where:
* ind = DstRegisterInd.File
* [2] = DstRegisterInd.Index
* .x = DstRegisterInd.SwizzleX
* ind = Indirect.File
* [2] = Indirect.Index
* .x = Indirect.SwizzleX
*/
if (reg->DstRegister.Indirect) {
if (reg->Register.Indirect) {
union tgsi_exec_channel index;
union tgsi_exec_channel indir_index;
uint swizzle;
@ -1441,15 +1437,15 @@ store_dest(
index.i[0] =
index.i[1] =
index.i[2] =
index.i[3] = reg->DstRegisterInd.Index;
index.i[3] = reg->Indirect.Index;
/* get current value of address register[swizzle] */
swizzle = tgsi_util_get_src_register_swizzle( &reg->DstRegisterInd, CHAN_X );
swizzle = tgsi_util_get_src_register_swizzle( &reg->Indirect, CHAN_X );
/* fetch values from the address/indirection register */
fetch_src_file_channel(
mach,
reg->DstRegisterInd.File,
reg->Indirect.File,
swizzle,
&index,
&indir_index );
@ -1458,37 +1454,37 @@ store_dest(
offset = (int) indir_index.f[0];
}
switch (reg->DstRegister.File) {
switch (reg->Register.File) {
case TGSI_FILE_NULL:
dst = &null;
break;
case TGSI_FILE_OUTPUT:
index = mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
+ reg->DstRegister.Index;
+ reg->Register.Index;
dst = &mach->Outputs[offset + index].xyzw[chan_index];
break;
case TGSI_FILE_TEMPORARY:
index = reg->DstRegister.Index;
index = reg->Register.Index;
assert( index < TGSI_EXEC_NUM_TEMPS );
dst = &mach->Temps[offset + index].xyzw[chan_index];
break;
case TGSI_FILE_ADDRESS:
index = reg->DstRegister.Index;
index = reg->Register.Index;
dst = &mach->Addrs[index].xyzw[chan_index];
break;
case TGSI_FILE_LOOP:
assert(reg->DstRegister.Index == 0);
assert(reg->Register.Index == 0);
assert(mach->LoopCounterStackTop > 0);
assert(chan_index == CHAN_X);
dst = &mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[chan_index];
break;
case TGSI_FILE_PREDICATE:
index = reg->DstRegister.Index;
index = reg->Register.Index;
assert(index < TGSI_EXEC_NUM_PREDS);
dst = &mach->Predicates[index].xyzw[chan_index];
break;
@ -1504,27 +1500,27 @@ store_dest(
switch (chan_index) {
case CHAN_X:
swizzle = inst->InstructionPredicate.SwizzleX;
swizzle = inst->Predicate.SwizzleX;
break;
case CHAN_Y:
swizzle = inst->InstructionPredicate.SwizzleY;
swizzle = inst->Predicate.SwizzleY;
break;
case CHAN_Z:
swizzle = inst->InstructionPredicate.SwizzleZ;
swizzle = inst->Predicate.SwizzleZ;
break;
case CHAN_W:
swizzle = inst->InstructionPredicate.SwizzleW;
swizzle = inst->Predicate.SwizzleW;
break;
default:
assert(0);
return;
}
assert(inst->InstructionPredicate.Index == 0);
assert(inst->Predicate.Index == 0);
pred = &mach->Predicates[inst->InstructionPredicate.Index].xyzw[swizzle];
pred = &mach->Predicates[inst->Predicate.Index].xyzw[swizzle];
if (inst->InstructionPredicate.Negate) {
if (inst->Predicate.Negate) {
for (i = 0; i < QUAD_SIZE; i++) {
if (pred->u[i]) {
execmask &= ~(1 << i);
@ -1576,10 +1572,10 @@ store_dest(
}
#define FETCH(VAL,INDEX,CHAN)\
fetch_source (mach, VAL, &inst->FullSrcRegisters[INDEX], CHAN)
fetch_source (mach, VAL, &inst->Src[INDEX], CHAN)
#define STORE(VAL,INDEX,CHAN)\
store_dest (mach, VAL, &inst->FullDstRegisters[INDEX], inst, CHAN )
store_dest (mach, VAL, &inst->Dst[INDEX], inst, CHAN )
/**
@ -1605,7 +1601,7 @@ exec_kil(struct tgsi_exec_machine *mach,
/* unswizzle channel */
swizzle = tgsi_util_get_full_src_register_swizzle (
&inst->FullSrcRegisters[0],
&inst->Src[0],
chan_index);
/* check if the component has not been already tested */
@ -1672,14 +1668,14 @@ exec_tex(struct tgsi_exec_machine *mach,
boolean biasLod,
boolean projected)
{
const uint unit = inst->FullSrcRegisters[1].SrcRegister.Index;
const uint unit = inst->Src[1].Register.Index;
union tgsi_exec_channel r[4];
uint chan_index;
float lodBias;
/* debug_printf("Sampler %u unit %u\n", sampler, unit); */
switch (inst->InstructionExtTexture.Texture) {
switch (inst->Texture.Texture) {
case TGSI_TEXTURE_1D:
case TGSI_TEXTURE_SHADOW1D:
@ -1769,7 +1765,7 @@ static void
exec_txd(struct tgsi_exec_machine *mach,
const struct tgsi_full_instruction *inst)
{
const uint unit = inst->FullSrcRegisters[3].SrcRegister.Index;
const uint unit = inst->Src[3].Register.Index;
union tgsi_exec_channel r[4];
uint chan_index;
@ -1777,7 +1773,7 @@ exec_txd(struct tgsi_exec_machine *mach,
* XXX: This is fake TXD -- the derivatives are not taken into account, yet.
*/
switch (inst->InstructionExtTexture.Texture) {
switch (inst->Texture.Texture) {
case TGSI_TEXTURE_1D:
case TGSI_TEXTURE_SHADOW1D:
@ -1899,20 +1895,20 @@ exec_declaration(struct tgsi_exec_machine *mach,
if (decl->Declaration.File == TGSI_FILE_INPUT) {
uint first, last, mask;
first = decl->DeclarationRange.First;
last = decl->DeclarationRange.Last;
first = decl->Range.First;
last = decl->Range.Last;
mask = decl->Declaration.UsageMask;
if (decl->Semantic.SemanticName == TGSI_SEMANTIC_POSITION) {
assert(decl->Semantic.SemanticIndex == 0);
if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
assert(decl->Semantic.Index == 0);
assert(first == last);
assert(mask = TGSI_WRITEMASK_XYZW);
mach->Inputs[first] = mach->QuadPos;
} else if (decl->Semantic.SemanticName == TGSI_SEMANTIC_FACE) {
} else if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
uint i;
assert(decl->Semantic.SemanticIndex == 0);
assert(decl->Semantic.Index == 0);
assert(first == last);
for (i = 0; i < QUAD_SIZE; i++) {
@ -2744,7 +2740,7 @@ exec_instruction(
mach->FuncStack[mach->FuncStackTop++] = mach->FuncMask;
/* Finally, jump to the subroutine */
*pc = inst->InstructionExtLabel.Label;
*pc = inst->Label.Label;
}
break;

1
src/gallium/auxiliary/tgsi/tgsi_iterate.c
View file

@ -39,7 +39,6 @@ tgsi_iterate_shader(
return FALSE;
ctx->processor = parse.FullHeader.Processor;
ctx->version = parse.FullVersion.Version;
if (ctx->prolog)
if (!ctx->prolog( ctx ))

1
src/gallium/auxiliary/tgsi/tgsi_iterate.h
View file

@ -61,7 +61,6 @@ struct tgsi_iterate_context
struct tgsi_iterate_context *ctx );
struct tgsi_processor processor;
struct tgsi_version version;
};
boolean

155
src/gallium/auxiliary/tgsi/tgsi_parse.c
View file

@ -28,44 +28,23 @@
#include "util/u_debug.h"
#include "pipe/p_shader_tokens.h"
#include "tgsi_parse.h"
#include "tgsi_build.h"
#include "util/u_memory.h"
void
tgsi_full_token_init(
union tgsi_full_token *full_token )
{
full_token->Token.Type = TGSI_TOKEN_TYPE_DECLARATION;
}
void
tgsi_full_token_free(
union tgsi_full_token *full_token )
{
}
unsigned
tgsi_parse_init(
struct tgsi_parse_context *ctx,
const struct tgsi_token *tokens )
{
ctx->FullVersion.Version = *(struct tgsi_version *) &tokens[0];
if( ctx->FullVersion.Version.MajorVersion > 1 ) {
ctx->FullHeader.Header = *(struct tgsi_header *) &tokens[0];
if( ctx->FullHeader.Header.HeaderSize >= 2 ) {
ctx->FullHeader.Processor = *(struct tgsi_processor *) &tokens[1];
}
else {
return TGSI_PARSE_ERROR;
}
ctx->FullHeader.Header = *(struct tgsi_header *) &tokens[1];
if( ctx->FullHeader.Header.HeaderSize >= 2 ) {
ctx->FullHeader.Processor = *(struct tgsi_processor *) &tokens[2];
}
else {
ctx->FullHeader.Processor = tgsi_default_processor();
}
ctx->Tokens = tokens;
ctx->Position = 1 + ctx->FullHeader.Header.HeaderSize;
tgsi_full_token_init( &ctx->FullToken );
ctx->Position = ctx->FullHeader.Header.HeaderSize;
return TGSI_PARSE_OK;
}
@ -74,7 +53,6 @@ void
tgsi_parse_free(
struct tgsi_parse_context *ctx )
{
tgsi_full_token_free( &ctx->FullToken );
}
boolean
@ -119,9 +97,6 @@ tgsi_parse_token(
struct tgsi_token token;
unsigned i;
tgsi_full_token_free( &ctx->FullToken );
tgsi_full_token_init( &ctx->FullToken );
next_token( ctx, &token );
switch( token.Type ) {
@ -129,10 +104,10 @@ tgsi_parse_token(
{
struct tgsi_full_declaration *decl = &ctx->FullToken.FullDeclaration;
*decl = tgsi_default_full_declaration();
memset(decl, 0, sizeof *decl);
copy_token(&decl->Declaration, &token);
next_token( ctx, &decl->DeclarationRange );
next_token( ctx, &decl->Range );
if( decl->Declaration.Semantic ) {
next_token( ctx, &decl->Semantic );
@ -145,9 +120,8 @@ tgsi_parse_token(
{
struct tgsi_full_immediate *imm = &ctx->FullToken.FullImmediate;
*imm = tgsi_default_full_immediate();
memset(imm, 0, sizeof *imm);
copy_token(&imm->Immediate, &token);
assert( !imm->Immediate.Extended );
switch (imm->Immediate.DataType) {
case TGSI_IMM_FLOAT32:
@ -169,137 +143,76 @@ tgsi_parse_token(
case TGSI_TOKEN_TYPE_INSTRUCTION:
{
struct tgsi_full_instruction *inst = &ctx->FullToken.FullInstruction;
unsigned extended;
*inst = tgsi_default_full_instruction();
memset(inst, 0, sizeof *inst);
copy_token(&inst->Instruction, &token);
extended = inst->Instruction.Extended;
if (inst->Instruction.Predicate) {
next_token(ctx, &inst->InstructionPredicate);
next_token(ctx, &inst->Predicate);
}
while( extended ) {
struct tgsi_src_register_ext token;
if (inst->Instruction.Label) {
next_token( ctx, &inst->Label);
}
next_token( ctx, &token );
switch( token.Type ) {
case TGSI_INSTRUCTION_EXT_TYPE_LABEL:
copy_token(&inst->InstructionExtLabel, &token);
break;
case TGSI_INSTRUCTION_EXT_TYPE_TEXTURE:
copy_token(&inst->InstructionExtTexture, &token);
break;
default:
assert( 0 );
}
extended = token.Extended;
if (inst->Instruction.Texture) {
next_token( ctx, &inst->Texture);
}
assert( inst->Instruction.NumDstRegs <= TGSI_FULL_MAX_DST_REGISTERS );
for( i = 0; i < inst->Instruction.NumDstRegs; i++ ) {
unsigned extended;
next_token( ctx, &inst->FullDstRegisters[i].DstRegister );
next_token( ctx, &inst->Dst[i].Register );
/*
* No support for indirect or multi-dimensional addressing.
*/
assert( !inst->FullDstRegisters[i].DstRegister.Dimension );
assert( !inst->Dst[i].Register.Dimension );
extended = inst->FullDstRegisters[i].DstRegister.Extended;
while( extended ) {
struct tgsi_src_register_ext token;
next_token( ctx, &token );
switch( token.Type ) {
case TGSI_DST_REGISTER_EXT_TYPE_MODULATE:
copy_token(&inst->FullDstRegisters[i].DstRegisterExtModulate,
&token);
break;
default:
assert( 0 );
}
extended = token.Extended;
}
if( inst->FullDstRegisters[i].DstRegister.Indirect ) {
next_token( ctx, &inst->FullDstRegisters[i].DstRegisterInd );
if( inst->Dst[i].Register.Indirect ) {
next_token( ctx, &inst->Dst[i].Indirect );
/*
* No support for indirect or multi-dimensional addressing.
*/
assert( !inst->FullDstRegisters[i].DstRegisterInd.Indirect );
assert( !inst->FullDstRegisters[i].DstRegisterInd.Dimension );
assert( !inst->FullDstRegisters[i].DstRegisterInd.Extended );
assert( !inst->Dst[i].Indirect.Dimension );
assert( !inst->Dst[i].Indirect.Indirect );
}
}
assert( inst->Instruction.NumSrcRegs <= TGSI_FULL_MAX_SRC_REGISTERS );
for( i = 0; i < inst->Instruction.NumSrcRegs; i++ ) {
unsigned extended;
next_token( ctx, &inst->FullSrcRegisters[i].SrcRegister );
next_token( ctx, &inst->Src[i].Register );
extended = inst->FullSrcRegisters[i].SrcRegister.Extended;
while( extended ) {
struct tgsi_src_register_ext token;
next_token( ctx, &token );
switch( token.Type ) {
case TGSI_SRC_REGISTER_EXT_TYPE_MOD:
copy_token(&inst->FullSrcRegisters[i].SrcRegisterExtMod,
&token);
break;
default:
assert( 0 );
}
extended = token.Extended;
}
if( inst->FullSrcRegisters[i].SrcRegister.Indirect ) {
next_token( ctx, &inst->FullSrcRegisters[i].SrcRegisterInd );
if( inst->Src[i].Register.Indirect ) {
next_token( ctx, &inst->Src[i].Indirect );
/*
* No support for indirect or multi-dimensional addressing.
*/
assert( !inst->FullSrcRegisters[i].SrcRegisterInd.Indirect );
assert( !inst->FullSrcRegisters[i].SrcRegisterInd.Dimension );
assert( !inst->FullSrcRegisters[i].SrcRegisterInd.Extended );
assert( !inst->Src[i].Indirect.Indirect );
assert( !inst->Src[i].Indirect.Dimension );
}
if( inst->FullSrcRegisters[i].SrcRegister.Dimension ) {
next_token( ctx, &inst->FullSrcRegisters[i].SrcRegisterDim );
if( inst->Src[i].Register.Dimension ) {
next_token( ctx, &inst->Src[i].Dimension );
/*
* No support for multi-dimensional addressing.
*/
assert( !inst->FullSrcRegisters[i].SrcRegisterDim.Dimension );
assert( !inst->FullSrcRegisters[i].SrcRegisterDim.Extended );
assert( !inst->Src[i].Dimension.Dimension );
if( inst->FullSrcRegisters[i].SrcRegisterDim.Indirect ) {
next_token( ctx, &inst->FullSrcRegisters[i].SrcRegisterDimInd );
if( inst->Src[i].Dimension.Indirect ) {
next_token( ctx, &inst->Src[i].DimIndirect );
/*
* No support for indirect or multi-dimensional addressing.
*/
assert( !inst->FullSrcRegisters[i].SrcRegisterInd.Indirect );
assert( !inst->FullSrcRegisters[i].SrcRegisterInd.Dimension );
assert( !inst->FullSrcRegisters[i].SrcRegisterInd.Extended );
assert( !inst->Src[i].Indirect.Indirect );
assert( !inst->Src[i].Indirect.Dimension );
}
}
}

41
src/gallium/auxiliary/tgsi/tgsi_parse.h
View file

@ -34,11 +34,6 @@
extern "C" {
#endif
struct tgsi_full_version
{
struct tgsi_version Version;
};
struct tgsi_full_header
{
struct tgsi_header Header;
@ -47,24 +42,22 @@ struct tgsi_full_header
struct tgsi_full_dst_register
{
struct tgsi_dst_register DstRegister;
struct tgsi_src_register DstRegisterInd;
struct tgsi_dst_register_ext_modulate DstRegisterExtModulate;
struct tgsi_dst_register Register;
struct tgsi_src_register Indirect;
};
struct tgsi_full_src_register
{
struct tgsi_src_register SrcRegister;
struct tgsi_src_register_ext_mod SrcRegisterExtMod;
struct tgsi_src_register SrcRegisterInd;
struct tgsi_dimension SrcRegisterDim;
struct tgsi_src_register SrcRegisterDimInd;
struct tgsi_src_register Register;
struct tgsi_src_register Indirect;
struct tgsi_dimension Dimension;
struct tgsi_src_register DimIndirect;
};
struct tgsi_full_declaration
{
struct tgsi_declaration Declaration;
struct tgsi_declaration_range DeclarationRange;
struct tgsi_declaration_range Range;
struct tgsi_declaration_semantic Semantic;
};
@ -80,12 +73,11 @@ struct tgsi_full_immediate
struct tgsi_full_instruction
{
struct tgsi_instruction Instruction;
struct tgsi_instruction_predicate InstructionPredicate;
struct tgsi_instruction_ext_label InstructionExtLabel;
struct tgsi_instruction_ext_texture InstructionExtTexture;
struct tgsi_full_dst_register FullDstRegisters[TGSI_FULL_MAX_DST_REGISTERS];
struct tgsi_full_src_register FullSrcRegisters[TGSI_FULL_MAX_SRC_REGISTERS];
uint Flags; /**< user-defined usage */
struct tgsi_instruction_predicate Predicate;
struct tgsi_instruction_label Label;
struct tgsi_instruction_texture Texture;
struct tgsi_full_dst_register Dst[TGSI_FULL_MAX_DST_REGISTERS];
struct tgsi_full_src_register Src[TGSI_FULL_MAX_SRC_REGISTERS];
};
union tgsi_full_token
@ -96,19 +88,10 @@ union tgsi_full_token
struct tgsi_full_instruction FullInstruction;
};
void
tgsi_full_token_init(
union tgsi_full_token *full_token );
void
tgsi_full_token_free(
union tgsi_full_token *full_token );
struct tgsi_parse_context
{
const struct tgsi_token *Tokens;
unsigned Position;
struct tgsi_full_version FullVersion;
struct tgsi_full_header FullHeader;
union tgsi_full_token FullToken;
};

48
src/gallium/auxiliary/tgsi/tgsi_ppc.c
View file

@ -60,7 +60,7 @@ const float ppc_builtin_constants[] ALIGN16_ATTRIB = {
for (CHAN = 0; CHAN < NUM_CHANNELS; CHAN++)
#define IS_DST0_CHANNEL_ENABLED( INST, CHAN )\
((INST).FullDstRegisters[0].DstRegister.WriteMask & (1 << (CHAN)))
((INST).Dst[0].Register.WriteMask & (1 << (CHAN)))
#define IF_IS_DST0_CHANNEL_ENABLED( INST, CHAN )\
if (IS_DST0_CHANNEL_ENABLED( INST, CHAN ))
@ -156,8 +156,8 @@ init_gen_context(struct gen_context *gen, struct ppc_function *func)
static boolean
is_ppc_vec_temporary(const struct tgsi_full_src_register *reg)
{
return (reg->SrcRegister.File == TGSI_FILE_TEMPORARY &&
reg->SrcRegister.Index < MAX_PPC_TEMPS);
return (reg->Register.File == TGSI_FILE_TEMPORARY &&
reg->Register.Index < MAX_PPC_TEMPS);
}
@ -167,8 +167,8 @@ is_ppc_vec_temporary(const struct tgsi_full_src_register *reg)
static boolean
is_ppc_vec_temporary_dst(const struct tgsi_full_dst_register *reg)
{
return (reg->DstRegister.File == TGSI_FILE_TEMPORARY &&
reg->DstRegister.Index < MAX_PPC_TEMPS);
return (reg->Register.File == TGSI_FILE_TEMPORARY &&
reg->Register.Index < MAX_PPC_TEMPS);
}
@ -291,10 +291,10 @@ emit_fetch(struct gen_context *gen,
case TGSI_SWIZZLE_Y:
case TGSI_SWIZZLE_Z:
case TGSI_SWIZZLE_W:
switch (reg->SrcRegister.File) {
switch (reg->Register.File) {
case TGSI_FILE_INPUT:
{
int offset = (reg->SrcRegister.Index * 4 + swizzle) * 16;
int offset = (reg->Register.Index * 4 + swizzle) * 16;
int offset_reg = emit_li_offset(gen, offset);
dst_vec = ppc_allocate_vec_register(gen->f);
ppc_lvx(gen->f, dst_vec, gen->inputs_reg, offset_reg);
@ -303,11 +303,11 @@ emit_fetch(struct gen_context *gen,
case TGSI_FILE_TEMPORARY:
if (is_ppc_vec_temporary(reg)) {
/* use PPC vec register */
dst_vec = gen->temps_map[reg->SrcRegister.Index][swizzle];
dst_vec = gen->temps_map[reg->Register.Index][swizzle];
}
else {
/* use memory-based temp register "file" */
int offset = (reg->SrcRegister.Index * 4 + swizzle) * 16;
int offset = (reg->Register.Index * 4 + swizzle) * 16;
int offset_reg = emit_li_offset(gen, offset);
dst_vec = ppc_allocate_vec_register(gen->f);
ppc_lvx(gen->f, dst_vec, gen->temps_reg, offset_reg);
@ -315,7 +315,7 @@ emit_fetch(struct gen_context *gen,
break;
case TGSI_FILE_IMMEDIATE:
{
int offset = (reg->SrcRegister.Index * 4 + swizzle) * 4;
int offset = (reg->Register.Index * 4 + swizzle) * 4;
int offset_reg = emit_li_offset(gen, offset);
dst_vec = ppc_allocate_vec_register(gen->f);
/* Load 4-byte word into vector register.
@ -331,7 +331,7 @@ emit_fetch(struct gen_context *gen,
break;
case TGSI_FILE_CONSTANT:
{
int offset = (reg->SrcRegister.Index * 4 + swizzle) * 4;
int offset = (reg->Register.Index * 4 + swizzle) * 4;
int offset_reg = emit_li_offset(gen, offset);
dst_vec = ppc_allocate_vec_register(gen->f);
/* Load 4-byte word into vector register.
@ -404,9 +404,9 @@ equal_src_locs(const struct tgsi_full_src_register *a, uint chan_a,
{
int swz_a, swz_b;
int sign_a, sign_b;
if (a->SrcRegister.File != b->SrcRegister.File)
if (a->Register.File != b->Register.File)
return FALSE;
if (a->SrcRegister.Index != b->SrcRegister.Index)
if (a->Register.Index != b->Register.Index)
return FALSE;
swz_a = tgsi_util_get_full_src_register_swizzle(a, chan_a);
swz_b = tgsi_util_get_full_src_register_swizzle(b, chan_b);
@ -431,7 +431,7 @@ get_src_vec(struct gen_context *gen,
struct tgsi_full_instruction *inst, int src_reg, uint chan)
{
const const struct tgsi_full_src_register *src =
&inst->FullSrcRegisters[src_reg];
&inst->Src[src_reg];
int vec;
uint i;
@ -482,10 +482,10 @@ get_dst_vec(struct gen_context *gen,
const struct tgsi_full_instruction *inst,
unsigned chan_index)
{
const struct tgsi_full_dst_register *reg = &inst->FullDstRegisters[0];
const struct tgsi_full_dst_register *reg = &inst->Dst[0];
if (is_ppc_vec_temporary_dst(reg)) {
int vec = gen->temps_map[reg->DstRegister.Index][chan_index];
int vec = gen->temps_map[reg->Register.Index][chan_index];
return vec;
}
else {
@ -505,12 +505,12 @@ emit_store(struct gen_context *gen,
unsigned chan_index,
boolean free_vec)
{
const struct tgsi_full_dst_register *reg = &inst->FullDstRegisters[0];
const struct tgsi_full_dst_register *reg = &inst->Dst[0];
switch (reg->DstRegister.File) {
switch (reg->Register.File) {
case TGSI_FILE_OUTPUT:
{
int offset = (reg->DstRegister.Index * 4 + chan_index) * 16;
int offset = (reg->Register.Index * 4 + chan_index) * 16;
int offset_reg = emit_li_offset(gen, offset);
ppc_stvx(gen->f, src_vec, gen->outputs_reg, offset_reg);
}
@ -518,14 +518,14 @@ emit_store(struct gen_context *gen,
case TGSI_FILE_TEMPORARY:
if (is_ppc_vec_temporary_dst(reg)) {
if (!free_vec) {
int dst_vec = gen->temps_map[reg->DstRegister.Index][chan_index];
int dst_vec = gen->temps_map[reg->Register.Index][chan_index];
if (dst_vec != src_vec)
ppc_vmove(gen->f, dst_vec, src_vec);
}
free_vec = FALSE;
}
else {
int offset = (reg->DstRegister.Index * 4 + chan_index) * 16;
int offset = (reg->Register.Index * 4 + chan_index) * 16;
int offset_reg = emit_li_offset(gen, offset);
ppc_stvx(gen->f, src_vec, gen->temps_reg, offset_reg);
}
@ -535,7 +535,7 @@ emit_store(struct gen_context *gen,
emit_addrs(
func,
xmm,
reg->DstRegister.Index,
reg->Register.Index,
chan_index );
break;
#endif
@ -1178,8 +1178,8 @@ emit_declaration(
unsigned first, last, mask;
unsigned i, j;
first = decl->DeclarationRange.First;
last = decl->DeclarationRange.Last;
first = decl->Range.First;
last = decl->Range.Last;
mask = decl->Declaration.UsageMask;
for( i = first; i <= last; i++ ) {

26
src/gallium/auxiliary/tgsi/tgsi_sanity.c
View file

@ -212,24 +212,24 @@ iter_instruction(
for (i = 0; i < inst->Instruction.NumDstRegs; i++) {
check_register_usage(
ctx,
inst->FullDstRegisters[i].DstRegister.File,
inst->FullDstRegisters[i].DstRegister.Index,
inst->Dst[i].Register.File,
inst->Dst[i].Register.Index,
"destination",
FALSE );
}
for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
check_register_usage(
ctx,
inst->FullSrcRegisters[i].SrcRegister.File,
inst->FullSrcRegisters[i].SrcRegister.Index,
inst->Src[i].Register.File,
inst->Src[i].Register.Index,
"source",
(boolean)inst->FullSrcRegisters[i].SrcRegister.Indirect );
if (inst->FullSrcRegisters[i].SrcRegister.Indirect) {
(boolean)inst->Src[i].Register.Indirect );
if (inst->Src[i].Register.Indirect) {
uint file;
int index;
file = inst->FullSrcRegisters[i].SrcRegisterInd.File;
index = inst->FullSrcRegisters[i].SrcRegisterInd.Index;
file = inst->Src[i].Indirect.File;
index = inst->Src[i].Indirect.Index;
check_register_usage(
ctx,
file,
@ -245,8 +245,8 @@ iter_instruction(
switch (inst->Instruction.Opcode) {
case TGSI_OPCODE_BGNFOR:
case TGSI_OPCODE_ENDFOR:
if (inst->FullDstRegisters[0].DstRegister.File != TGSI_FILE_LOOP ||
inst->FullDstRegisters[0].DstRegister.Index != 0) {
if (inst->Dst[0].Register.File != TGSI_FILE_LOOP ||
inst->Dst[0].Register.Index != 0) {
report_error(ctx, "Destination register must be LOOP[0]");
}
break;
@ -254,8 +254,8 @@ iter_instruction(
switch (inst->Instruction.Opcode) {
case TGSI_OPCODE_BGNFOR:
if (inst->FullSrcRegisters[0].SrcRegister.File != TGSI_FILE_CONSTANT &&
inst->FullSrcRegisters[0].SrcRegister.File != TGSI_FILE_IMMEDIATE) {
if (inst->Src[0].Register.File != TGSI_FILE_CONSTANT &&
inst->Src[0].Register.File != TGSI_FILE_IMMEDIATE) {
report_error(ctx, "Source register file must be either CONST or IMM");
}
break;
@ -286,7 +286,7 @@ iter_declaration(
file = decl->Declaration.File;
if (!check_file_name( ctx, file ))
return TRUE;
for (i = decl->DeclarationRange.First; i <= decl->DeclarationRange.Last; i++) {
for (i = decl->Range.First; i <= decl->Range.Last; i++) {
if (is_register_declared( ctx, file, i ))
report_error( ctx, "%s[%u]: The same register declared more than once", file_names[file], i );
ctx->regs_decl[file][i / BITS_IN_REG_FLAG] |= (1 << (i % BITS_IN_REG_FLAG));

53
src/gallium/auxiliary/tgsi/tgsi_scan.c
View file

@ -35,7 +35,6 @@
#include "util/u_math.h"
#include "tgsi/tgsi_build.h"
#include "tgsi/tgsi_parse.h"
#include "tgsi/tgsi_scan.h"
@ -97,14 +96,14 @@ tgsi_scan_shader(const struct tgsi_token *tokens,
uint i;
for (i = 0; i < fullinst->Instruction.NumSrcRegs; i++) {
const struct tgsi_full_src_register *src =
&fullinst->FullSrcRegisters[i];
if (src->SrcRegister.File == TGSI_FILE_INPUT) {
const int ind = src->SrcRegister.Index;
&fullinst->Src[i];
if (src->Register.File == TGSI_FILE_INPUT) {
const int ind = src->Register.Index;
if (info->input_semantic_name[ind] == TGSI_SEMANTIC_FOG) {
if (src->SrcRegister.SwizzleX == TGSI_SWIZZLE_X) {
if (src->Register.SwizzleX == TGSI_SWIZZLE_X) {
info->uses_fogcoord = TRUE;
}
else if (src->SrcRegister.SwizzleX == TGSI_SWIZZLE_Y) {
else if (src->Register.SwizzleX == TGSI_SWIZZLE_Y) {
info->uses_frontfacing = TRUE;
}
}
@ -120,8 +119,8 @@ tgsi_scan_shader(const struct tgsi_token *tokens,
= &parse.FullToken.FullDeclaration;
const uint file = fulldecl->Declaration.File;
uint reg;
for (reg = fulldecl->DeclarationRange.First;
reg <= fulldecl->DeclarationRange.Last;
for (reg = fulldecl->Range.First;
reg <= fulldecl->Range.Last;
reg++) {
/* only first 32 regs will appear in this bitfield */
@ -130,21 +129,21 @@ tgsi_scan_shader(const struct tgsi_token *tokens,
info->file_max[file] = MAX2(info->file_max[file], (int)reg);
if (file == TGSI_FILE_INPUT) {
info->input_semantic_name[reg] = (ubyte)fulldecl->Semantic.SemanticName;
info->input_semantic_index[reg] = (ubyte)fulldecl->Semantic.SemanticIndex;
info->input_semantic_name[reg] = (ubyte)fulldecl->Semantic.Name;
info->input_semantic_index[reg] = (ubyte)fulldecl->Semantic.Index;
info->input_interpolate[reg] = (ubyte)fulldecl->Declaration.Interpolate;
info->num_inputs++;
}
else if (file == TGSI_FILE_OUTPUT) {
info->output_semantic_name[reg] = (ubyte)fulldecl->Semantic.SemanticName;
info->output_semantic_index[reg] = (ubyte)fulldecl->Semantic.SemanticIndex;
info->output_semantic_name[reg] = (ubyte)fulldecl->Semantic.Name;
info->output_semantic_index[reg] = (ubyte)fulldecl->Semantic.Index;
info->num_outputs++;
}
/* special case */
if (procType == TGSI_PROCESSOR_FRAGMENT &&
file == TGSI_FILE_OUTPUT &&
fulldecl->Semantic.SemanticName == TGSI_SEMANTIC_POSITION) {
fulldecl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
info->writes_z = TRUE;
}
}
@ -206,29 +205,25 @@ tgsi_is_passthrough_shader(const struct tgsi_token *tokens)
struct tgsi_full_instruction *fullinst =
&parse.FullToken.FullInstruction;
const struct tgsi_full_src_register *src =
&fullinst->FullSrcRegisters[0];
&fullinst->Src[0];
const struct tgsi_full_dst_register *dst =
&fullinst->FullDstRegisters[0];
&fullinst->Dst[0];
/* Do a whole bunch of checks for a simple move */
if (fullinst->Instruction.Opcode != TGSI_OPCODE_MOV ||
src->SrcRegister.File != TGSI_FILE_INPUT ||
dst->DstRegister.File != TGSI_FILE_OUTPUT ||
src->SrcRegister.Index != dst->DstRegister.Index ||
src->Register.File != TGSI_FILE_INPUT ||
dst->Register.File != TGSI_FILE_OUTPUT ||
src->Register.Index != dst->Register.Index ||
src->SrcRegister.Negate ||
src->SrcRegisterExtMod.Negate ||
src->SrcRegisterExtMod.Absolute ||
src->SrcRegisterExtMod.Scale2X ||
src->SrcRegisterExtMod.Bias ||
src->SrcRegisterExtMod.Complement ||
src->Register.Negate ||
src->Register.Absolute ||
src->SrcRegister.SwizzleX != TGSI_SWIZZLE_X ||
src->SrcRegister.SwizzleY != TGSI_SWIZZLE_Y ||
src->SrcRegister.SwizzleZ != TGSI_SWIZZLE_Z ||
src->SrcRegister.SwizzleW != TGSI_SWIZZLE_W ||
src->Register.SwizzleX != TGSI_SWIZZLE_X ||
src->Register.SwizzleY != TGSI_SWIZZLE_Y ||
src->Register.SwizzleZ != TGSI_SWIZZLE_Z ||
src->Register.SwizzleW != TGSI_SWIZZLE_W ||
dst->DstRegister.WriteMask != TGSI_WRITEMASK_XYZW)
dst->Register.WriteMask != TGSI_WRITEMASK_XYZW)
{
tgsi_parse_free(&parse);
return FALSE;

53
src/gallium/auxiliary/tgsi/tgsi_sse2.c
View file

@ -58,7 +58,7 @@
for (CHAN = 0; CHAN < NUM_CHANNELS; CHAN++)
#define IS_DST0_CHANNEL_ENABLED( INST, CHAN )\
((INST).FullDstRegisters[0].DstRegister.WriteMask & (1 << (CHAN)))
((INST).Dst[0].Register.WriteMask & (1 << (CHAN)))
#define IF_IS_DST0_CHANNEL_ENABLED( INST, CHAN )\
if (IS_DST0_CHANNEL_ENABLED( INST, CHAN ))
@ -1267,23 +1267,23 @@ emit_fetch(
case TGSI_SWIZZLE_Y:
case TGSI_SWIZZLE_Z:
case TGSI_SWIZZLE_W:
switch (reg->SrcRegister.File) {
switch (reg->Register.File) {
case TGSI_FILE_CONSTANT:
emit_const(
func,
xmm,
reg->SrcRegister.Index,
reg->Register.Index,
swizzle,
reg->SrcRegister.Indirect,
reg->SrcRegisterInd.File,
reg->SrcRegisterInd.Index );
reg->Register.Indirect,
reg->Indirect.File,
reg->Indirect.Index );
break;
case TGSI_FILE_IMMEDIATE:
emit_immediate(
func,
xmm,
reg->SrcRegister.Index,
reg->Register.Index,
swizzle );
break;
@ -1291,7 +1291,7 @@ emit_fetch(
emit_inputf(
func,
xmm,
reg->SrcRegister.Index,
reg->Register.Index,
swizzle );
break;
@ -1299,7 +1299,7 @@ emit_fetch(
emit_tempf(
func,
xmm,
reg->SrcRegister.Index,
reg->Register.Index,
swizzle );
break;
@ -1331,7 +1331,7 @@ emit_fetch(
}
#define FETCH( FUNC, INST, XMM, INDEX, CHAN )\
emit_fetch( FUNC, XMM, &(INST).FullSrcRegisters[INDEX], CHAN )
emit_fetch( FUNC, XMM, &(INST).Src[INDEX], CHAN )
/**
* Register store.
@ -1371,12 +1371,12 @@ emit_store(
}
switch( reg->DstRegister.File ) {
switch( reg->Register.File ) {
case TGSI_FILE_OUTPUT:
emit_output(
func,
xmm,
reg->DstRegister.Index,
reg->Register.Index,
chan_index );
break;
@ -1384,7 +1384,7 @@ emit_store(
emit_temps(
func,
xmm,
reg->DstRegister.Index,
reg->Register.Index,
chan_index );
break;
@ -1392,7 +1392,7 @@ emit_store(
emit_addrs(
func,
xmm,
reg->DstRegister.Index,
reg->Register.Index,
chan_index );
break;
@ -1402,7 +1402,7 @@ emit_store(
}
#define STORE( FUNC, INST, XMM, INDEX, CHAN )\
emit_store( FUNC, XMM, &(INST).FullDstRegisters[INDEX], &(INST), CHAN )
emit_store( FUNC, XMM, &(INST).Dst[INDEX], &(INST), CHAN )
static void PIPE_CDECL
@ -1459,12 +1459,13 @@ emit_tex( struct x86_function *func,
boolean lodbias,
boolean projected)
{
const uint unit = inst->FullSrcRegisters[1].SrcRegister.Index;
const uint unit = inst->Src[1].Register.Index;
struct x86_reg args[2];
unsigned count;
unsigned i;
switch (inst->InstructionExtTexture.Texture) {
assert(inst->Instruction.Texture);
switch (inst->Texture.Texture) {
case TGSI_TEXTURE_1D:
count = 1;
break;
@ -1719,15 +1720,15 @@ indirect_temp_reference(const struct tgsi_full_instruction *inst)
{
uint i;
for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
const struct tgsi_full_src_register *reg = &inst->FullSrcRegisters[i];
if (reg->SrcRegister.File == TGSI_FILE_TEMPORARY &&
reg->SrcRegister.Indirect)
const struct tgsi_full_src_register *reg = &inst->Src[i];
if (reg->Register.File == TGSI_FILE_TEMPORARY &&
reg->Register.Indirect)
return TRUE;
}
for (i = 0; i < inst->Instruction.NumDstRegs; i++) {
const struct tgsi_full_dst_register *reg = &inst->FullDstRegisters[i];
if (reg->DstRegister.File == TGSI_FILE_TEMPORARY &&
reg->DstRegister.Indirect)
const struct tgsi_full_dst_register *reg = &inst->Dst[i];
if (reg->Register.File == TGSI_FILE_TEMPORARY &&
reg->Register.Indirect)
return TRUE;
}
return FALSE;
@ -2243,7 +2244,7 @@ emit_instruction(
case TGSI_OPCODE_KIL:
/* conditional kill */
emit_kil( func, &inst->FullSrcRegisters[0] );
emit_kil( func, &inst->Src[0] );
break;
case TGSI_OPCODE_PK2H:
@ -2636,8 +2637,8 @@ emit_declaration(
unsigned first, last, mask;
unsigned i, j;
first = decl->DeclarationRange.First;
last = decl->DeclarationRange.Last;
first = decl->Range.First;
last = decl->Range.Last;
mask = decl->Declaration.UsageMask;
for( i = first; i <= last; i++ ) {

217
src/gallium/auxiliary/tgsi/tgsi_text.c
View file

@ -172,29 +172,25 @@ static void report_error( struct translate_ctx *ctx, const char *msg )
/* Parse shader header.
* Return TRUE for one of the following headers.
* FRAG1.1
* GEOM1.1
* VERT1.1
* FRAG
* GEOM
* VERT
*/
static boolean parse_header( struct translate_ctx *ctx )
{
uint processor;
if (str_match_no_case( &ctx->cur, "FRAG1.1" ))
if (str_match_no_case( &ctx->cur, "FRAG" ))
processor = TGSI_PROCESSOR_FRAGMENT;
else if (str_match_no_case( &ctx->cur, "VERT1.1" ))
else if (str_match_no_case( &ctx->cur, "VERT" ))
processor = TGSI_PROCESSOR_VERTEX;
else if (str_match_no_case( &ctx->cur, "GEOM1.1" ))
else if (str_match_no_case( &ctx->cur, "GEOM" ))
processor = TGSI_PROCESSOR_GEOMETRY;
else {
report_error( ctx, "Unknown header" );
return FALSE;
}
if (ctx->tokens_cur >= ctx->tokens_end)
return FALSE;
*(struct tgsi_version *) ctx->tokens_cur++ = tgsi_build_version();
if (ctx->tokens_cur >= ctx->tokens_end)
return FALSE;
ctx->header = (struct tgsi_header *) ctx->tokens_cur++;
@ -486,16 +482,6 @@ parse_register_dcl(
return TRUE;
}
static const char *modulate_names[TGSI_MODULATE_COUNT] =
{
"_1X",
"_2X",
"_4X",
"_8X",
"_D2",
"_D4",
"_D8"
};
static boolean
parse_dst_operand(
@ -512,26 +498,13 @@ parse_dst_operand(
cur = ctx->cur;
eat_opt_white( &cur );
if (*cur == '_') {
uint i;
for (i = 0; i < TGSI_MODULATE_COUNT; i++) {
if (str_match_no_case( &cur, modulate_names[i] )) {
if (!is_digit_alpha_underscore( cur )) {
dst->DstRegisterExtModulate.Modulate = i;
ctx->cur = cur;
break;
}
}
}
}
if (!parse_opt_writemask( ctx, &writemask ))
return FALSE;
dst->DstRegister.File = file;
dst->DstRegister.Index = index;
dst->DstRegister.WriteMask = writemask;
dst->Register.File = file;
dst->Register.Index = index;
dst->Register.WriteMask = writemask;
return TRUE;
}
@ -577,162 +550,52 @@ parse_src_operand(
struct translate_ctx *ctx,
struct tgsi_full_src_register *src )
{
const char *cur;
float value;
uint file;
int index;
uint ind_file;
int ind_index;
uint ind_comp;
uint swizzle[4];
boolean parsed_ext_negate_paren = FALSE;
boolean parsed_swizzle;
if (*ctx->cur == '-') {
cur = ctx->cur;
cur++;
eat_opt_white( &cur );
if (*cur == '(') {
cur++;
src->SrcRegisterExtMod.Negate = 1;
eat_opt_white( &cur );
ctx->cur = cur;
parsed_ext_negate_paren = TRUE;
}
else if (*cur == '|') {
cur++;
src->SrcRegisterExtMod.Negate = 1;
src->SrcRegisterExtMod.Absolute = 1;
eat_opt_white(&cur);
ctx->cur = cur;
}
}
else if (*ctx->cur == '|') {
ctx->cur++;
eat_opt_white( &ctx->cur );
src->SrcRegisterExtMod.Absolute = 1;
src->Register.Negate = 1;
}
if (*ctx->cur == '-') {
if (*ctx->cur == '|') {
ctx->cur++;
eat_opt_white( &ctx->cur );
src->SrcRegister.Negate = 1;
}
cur = ctx->cur;
if (parse_float( &cur, &value )) {
if (value == 2.0f) {
eat_opt_white( &cur );
if (*cur != '*') {
report_error( ctx, "Expected `*'" );
return FALSE;
}
cur++;
if (*cur != '(') {
report_error( ctx, "Expected `('" );
return FALSE;
}
cur++;
src->SrcRegisterExtMod.Scale2X = 1;
eat_opt_white( &cur );
ctx->cur = cur;
}
}
if (*ctx->cur == '(') {
ctx->cur++;
eat_opt_white( &ctx->cur );
src->SrcRegisterExtMod.Bias = 1;
}
cur = ctx->cur;
if (parse_float( &cur, &value )) {
if (value == 1.0f) {
eat_opt_white( &cur );
if (*cur != '-') {
report_error( ctx, "Expected `-'" );
return FALSE;
}
cur++;
if (*cur != '(') {
report_error( ctx, "Expected `('" );
return FALSE;
}
cur++;
src->SrcRegisterExtMod.Complement = 1;
eat_opt_white( &cur );
ctx->cur = cur;
}
src->Register.Absolute = 1;
}
if (!parse_register_src(ctx, &file, &index, &ind_file, &ind_index, &ind_comp))
return FALSE;
src->SrcRegister.File = file;
src->SrcRegister.Index = index;
src->Register.File = file;
src->Register.Index = index;
if (ind_file != TGSI_FILE_NULL) {
src->SrcRegister.Indirect = 1;
src->SrcRegisterInd.File = ind_file;
src->SrcRegisterInd.Index = ind_index;
src->SrcRegisterInd.SwizzleX = ind_comp;
src->SrcRegisterInd.SwizzleY = ind_comp;
src->SrcRegisterInd.SwizzleZ = ind_comp;
src->SrcRegisterInd.SwizzleW = ind_comp;
src->Register.Indirect = 1;
src->Indirect.File = ind_file;
src->Indirect.Index = ind_index;
src->Indirect.SwizzleX = ind_comp;
src->Indirect.SwizzleY = ind_comp;
src->Indirect.SwizzleZ = ind_comp;
src->Indirect.SwizzleW = ind_comp;
}
/* Parse optional swizzle.
*/
if (parse_optional_swizzle( ctx, swizzle, &parsed_swizzle )) {
if (parsed_swizzle) {
src->SrcRegister.SwizzleX = swizzle[0];
src->SrcRegister.SwizzleY = swizzle[1];
src->SrcRegister.SwizzleZ = swizzle[2];
src->SrcRegister.SwizzleW = swizzle[3];
src->Register.SwizzleX = swizzle[0];
src->Register.SwizzleY = swizzle[1];
src->Register.SwizzleZ = swizzle[2];
src->Register.SwizzleW = swizzle[3];
}
}
if (src->SrcRegisterExtMod.Complement) {
eat_opt_white( &ctx->cur );
if (*ctx->cur != ')') {
report_error( ctx, "Expected `)'" );
return FALSE;
}
ctx->cur++;
}
if (src->SrcRegisterExtMod.Bias) {
eat_opt_white( &ctx->cur );
if (*ctx->cur != ')') {
report_error( ctx, "Expected `)'" );
return FALSE;
}
ctx->cur++;
eat_opt_white( &ctx->cur );
if (*ctx->cur != '-') {
report_error( ctx, "Expected `-'" );
return FALSE;
}
ctx->cur++;
eat_opt_white( &ctx->cur );
if (!parse_float( &ctx->cur, &value )) {
report_error( ctx, "Expected literal floating point" );
return FALSE;
}
if (value != 0.5f) {
report_error( ctx, "Expected 0.5" );
return FALSE;
}
}
if (src->SrcRegisterExtMod.Scale2X) {
eat_opt_white( &ctx->cur );
if (*ctx->cur != ')') {
report_error( ctx, "Expected `)'" );
return FALSE;
}
ctx->cur++;
}
if (src->SrcRegisterExtMod.Absolute) {
if (src->Register.Absolute) {
eat_opt_white( &ctx->cur );
if (*ctx->cur != '|') {
report_error( ctx, "Expected `|'" );
@ -741,14 +604,6 @@ parse_src_operand(
ctx->cur++;
}
if (parsed_ext_negate_paren) {
eat_opt_white( &ctx->cur );
if (*ctx->cur != ')') {
report_error( ctx, "Expected `)'" );
return FALSE;
}
ctx->cur++;
}
return TRUE;
}
@ -840,11 +695,11 @@ parse_instruction(
}
if (i < info->num_dst) {
if (!parse_dst_operand( ctx, &inst.FullDstRegisters[i] ))
if (!parse_dst_operand( ctx, &inst.Dst[i] ))
return FALSE;
}
else if (i < info->num_dst + info->num_src) {
if (!parse_src_operand( ctx, &inst.FullSrcRegisters[i - info->num_dst] ))
if (!parse_src_operand( ctx, &inst.Src[i - info->num_dst] ))
return FALSE;
}
else {
@ -853,7 +708,8 @@ parse_instruction(
for (j = 0; j < TGSI_TEXTURE_COUNT; j++) {
if (str_match_no_case( &ctx->cur, texture_names[j] )) {
if (!is_digit_alpha_underscore( ctx->cur )) {
inst.InstructionExtTexture.Texture = j;
inst.Instruction.Texture = 1;
inst.Texture.Texture = j;
break;
}
}
@ -879,7 +735,8 @@ parse_instruction(
report_error( ctx, "Expected a label" );
return FALSE;
}
inst.InstructionExtLabel.Label = target;
inst.Instruction.Label = 1;
inst.Label.Label = target;
}
advance = tgsi_build_full_instruction(
@ -938,8 +795,8 @@ static boolean parse_declaration( struct translate_ctx *ctx )
decl = tgsi_default_full_declaration();
decl.Declaration.File = file;
decl.Declaration.UsageMask = writemask;
decl.DeclarationRange.First = first;
decl.DeclarationRange.Last = last;
decl.Range.First = first;
decl.Range.Last = last;
cur = ctx->cur;
eat_opt_white( &cur );
@ -970,13 +827,13 @@ static boolean parse_declaration( struct translate_ctx *ctx )
}
cur2++;
decl.Semantic.SemanticIndex = index;
decl.Semantic.Index = index;
cur = cur2;
}
decl.Declaration.Semantic = 1;
decl.Semantic.SemanticName = i;
decl.Semantic.Name = i;
ctx->cur = cur;
break;

10
src/gallium/auxiliary/tgsi/tgsi_transform.c
View file

@ -130,15 +130,13 @@ tgsi_transform_shader(const struct tgsi_token *tokens_in,
/**
** Setup output shader
**/
*(struct tgsi_version *) &tokens_out[0] = tgsi_build_version();
ctx->header = (struct tgsi_header *) (tokens_out + 1);
ctx->header = (struct tgsi_header *)tokens_out;
*ctx->header = tgsi_build_header();
processor = (struct tgsi_processor *) (tokens_out + 2);
processor = (struct tgsi_processor *) (tokens_out + 1);
*processor = tgsi_build_processor( procType, ctx->header );
ctx->ti = 3;
ctx->ti = 2;
/**
@ -215,7 +213,7 @@ tgsi_transform_foo( struct tgsi_token *tokens_out,
uint max_tokens_out )
{
const char *text =
"FRAG1.1\n"
"FRAG\n"
"DCL IN[0], COLOR, CONSTANT\n"
"DCL OUT[0], COLOR\n"
" 0: MOV OUT[0], IN[0]\n"

55
src/gallium/auxiliary/tgsi/tgsi_ureg.c
View file

@ -37,7 +37,6 @@
#include "util/u_math.h"
union tgsi_any_token {
struct tgsi_version version;
struct tgsi_header header;
struct tgsi_processor processor;
struct tgsi_token token;
@ -48,13 +47,11 @@ union tgsi_any_token {
union tgsi_immediate_data imm_data;
struct tgsi_instruction insn;
struct tgsi_instruction_predicate insn_predicate;
struct tgsi_instruction_ext_label insn_ext_label;
struct tgsi_instruction_ext_texture insn_ext_texture;
struct tgsi_instruction_label insn_label;
struct tgsi_instruction_texture insn_texture;
struct tgsi_src_register src;
struct tgsi_src_register_ext_mod src_ext_mod;
struct tgsi_dimension dim;
struct tgsi_dst_register dst;
struct tgsi_dst_register_ext_modulate dst_ext_mod;
unsigned value;
};
@ -576,17 +573,8 @@ ureg_emit_src( struct ureg_program *ureg,
out[n].src.SwizzleW = src.SwizzleW;
out[n].src.Index = src.Index;
out[n].src.Negate = src.Negate;
out[0].src.Absolute = src.Absolute;
n++;
if (src.Absolute) {
out[0].src.Extended = 1;
out[0].src.Negate = 0;
out[n].value = 0;
out[n].src_ext_mod.Type = TGSI_SRC_REGISTER_EXT_TYPE_MOD;
out[n].src_ext_mod.Absolute = 1;
out[n].src_ext_mod.Negate = src.Negate;
n++;
}
if (src.Indirect) {
out[0].src.Indirect = 1;
@ -713,13 +701,11 @@ ureg_emit_label(struct ureg_program *ureg,
return;
out = get_tokens( ureg, DOMAIN_INSN, 1 );
insn = retrieve_token( ureg, DOMAIN_INSN, extended_token );
insn->token.Extended = 1;
out[0].value = 0;
out[0].insn_ext_label.Type = TGSI_INSTRUCTION_EXT_TYPE_LABEL;
insn = retrieve_token( ureg, DOMAIN_INSN, extended_token );
insn->insn.Label = 1;
*label_token = ureg->domain[DOMAIN_INSN].count - 1;
}
@ -742,8 +728,7 @@ ureg_fixup_label(struct ureg_program *ureg,
{
union tgsi_any_token *out = retrieve_token( ureg, DOMAIN_INSN, label_token );
assert(out->insn_ext_label.Type == TGSI_INSTRUCTION_EXT_TYPE_LABEL);
out->insn_ext_label.Label = instruction_number;
out->insn_label.Label = instruction_number;
}
@ -757,11 +742,10 @@ ureg_emit_texture(struct ureg_program *ureg,
out = get_tokens( ureg, DOMAIN_INSN, 1 );
insn = retrieve_token( ureg, DOMAIN_INSN, extended_token );
insn->token.Extended = 1;
insn->insn.Texture = 1;
out[0].value = 0;
out[0].insn_ext_texture.Type = TGSI_INSTRUCTION_EXT_TYPE_TEXTURE;
out[0].insn_ext_texture.Texture = target;
out[0].insn_texture.Texture = target;
}
@ -926,8 +910,8 @@ static void emit_decl( struct ureg_program *ureg,
out[1].decl_range.Last = index;
out[2].value = 0;
out[2].decl_semantic.SemanticName = semantic_name;
out[2].decl_semantic.SemanticIndex = semantic_index;
out[2].decl_semantic.Name = semantic_name;
out[2].decl_semantic.Index = semantic_index;
}
@ -962,7 +946,6 @@ static void emit_immediate( struct ureg_program *ureg,
out[0].imm.NrTokens = 5;
out[0].imm.DataType = TGSI_IMM_FLOAT32;
out[0].imm.Padding = 0;
out[0].imm.Extended = 0;
out[1].imm_data.Float = v[0];
out[2].imm_data.Float = v[1];
@ -1079,17 +1062,13 @@ fixup_header_size(struct ureg_program *ureg)
static void
emit_header( struct ureg_program *ureg )
{
union tgsi_any_token *out = get_tokens( ureg, DOMAIN_DECL, 3 );
union tgsi_any_token *out = get_tokens( ureg, DOMAIN_DECL, 2 );
out[0].version.MajorVersion = 1;
out[0].version.MinorVersion = 1;
out[0].version.Padding = 0;
out[0].header.HeaderSize = 2;
out[0].header.BodySize = 0;
out[1].header.HeaderSize = 2;
out[1].header.BodySize = 0;
out[2].processor.Processor = ureg->processor;
out[2].processor.Padding = 0;
out[1].processor.Processor = ureg->processor;
out[1].processor.Padding = 0;
}

38
src/gallium/auxiliary/tgsi/tgsi_util.c
View file

@ -76,7 +76,7 @@ tgsi_util_get_full_src_register_swizzle(
unsigned component )
{
return tgsi_util_get_src_register_swizzle(
&reg->SrcRegister,
&reg->Register,
component );
}
@ -111,10 +111,10 @@ tgsi_util_get_full_src_register_sign_mode(
{
unsigned sign_mode;
if( reg->SrcRegisterExtMod.Absolute ) {
if( reg->Register.Absolute ) {
/* Consider only the post-abs negation. */
if( reg->SrcRegisterExtMod.Negate ) {
if( reg->Register.Negate ) {
sign_mode = TGSI_UTIL_SIGN_SET;
}
else {
@ -122,17 +122,7 @@ tgsi_util_get_full_src_register_sign_mode(
}
}
else {
/* Accumulate the three negations. */
unsigned negate;
negate = reg->SrcRegister.Negate;
if( reg->SrcRegisterExtMod.Negate ) {
negate = !negate;
}
if( negate ) {
if( reg->Register.Negate ) {
sign_mode = TGSI_UTIL_SIGN_TOGGLE;
}
else {
@ -151,27 +141,23 @@ tgsi_util_set_full_src_register_sign_mode(
switch (sign_mode)
{
case TGSI_UTIL_SIGN_CLEAR:
reg->SrcRegister.Negate = 0;
reg->SrcRegisterExtMod.Absolute = 1;
reg->SrcRegisterExtMod.Negate = 0;
reg->Register.Negate = 0;
reg->Register.Absolute = 1;
break;
case TGSI_UTIL_SIGN_SET:
reg->SrcRegister.Negate = 0;
reg->SrcRegisterExtMod.Absolute = 1;
reg->SrcRegisterExtMod.Negate = 1;
reg->Register.Absolute = 1;
reg->Register.Negate = 1;
break;
case TGSI_UTIL_SIGN_TOGGLE:
reg->SrcRegister.Negate = 1;
reg->SrcRegisterExtMod.Absolute = 0;
reg->SrcRegisterExtMod.Negate = 0;
reg->Register.Negate = 1;
reg->Register.Absolute = 0;
break;
case TGSI_UTIL_SIGN_KEEP:
reg->SrcRegister.Negate = 0;
reg->SrcRegisterExtMod.Absolute = 0;
reg->SrcRegisterExtMod.Negate = 0;
reg->Register.Negate = 0;
reg->Register.Absolute = 0;
break;
default:

16
src/gallium/auxiliary/vl/vl_compositor.c
View file

@ -95,12 +95,11 @@ create_vert_shader(struct vl_compositor *c)
assert(c);
tokens = (struct tgsi_token*)MALLOC(max_tokens * sizeof(struct tgsi_token));
*(struct tgsi_version*)&tokens[0] = tgsi_build_version();
header = (struct tgsi_header*)&tokens[1];
header = (struct tgsi_header*)&tokens[0];
*header = tgsi_build_header();
*(struct tgsi_processor*)&tokens[2] = tgsi_build_processor(TGSI_PROCESSOR_VERTEX, header);
*(struct tgsi_processor*)&tokens[1] = tgsi_build_processor(TGSI_PROCESSOR_VERTEX, header);
ti = 3;
ti = 2;
/*
* decl i0 ; Vertex pos
@ -172,12 +171,11 @@ create_frag_shader(struct vl_compositor *c)
assert(c);
tokens = (struct tgsi_token*)MALLOC(max_tokens * sizeof(struct tgsi_token));
*(struct tgsi_version*)&tokens[0] = tgsi_build_version();
header = (struct tgsi_header*)&tokens[1];
header = (struct tgsi_header*)&tokens[0];
*header = tgsi_build_header();
*(struct tgsi_processor*)&tokens[2] = tgsi_build_processor(TGSI_PROCESSOR_FRAGMENT, header);
*(struct tgsi_processor*)&tokens[1] = tgsi_build_processor(TGSI_PROCESSOR_FRAGMENT, header);
ti = 3;
ti = 2;
/* decl i0 ; Texcoords for s0 */
decl = vl_decl_interpolated_input(TGSI_SEMANTIC_GENERIC, 1, 0, 0, TGSI_INTERPOLATE_LINEAR);
@ -213,7 +211,7 @@ create_frag_shader(struct vl_compositor *c)
*/
for (i = 0; i < 4; ++i) {
inst = vl_inst3(TGSI_OPCODE_DP4, TGSI_FILE_OUTPUT, 0, TGSI_FILE_TEMPORARY, 0, TGSI_FILE_CONSTANT, i);
inst.FullDstRegisters[0].DstRegister.WriteMask = TGSI_WRITEMASK_X << i;
inst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_X << i;
ti += tgsi_build_full_instruction(&inst, &tokens[ti], header, max_tokens - ti);
}

74
src/gallium/auxiliary/vl/vl_mpeg12_mc_renderer.c
View file

@ -115,12 +115,11 @@ create_intra_vert_shader(struct vl_mpeg12_mc_renderer *r)
assert(r);
tokens = (struct tgsi_token *) malloc(max_tokens * sizeof(struct tgsi_token));
*(struct tgsi_version *) &tokens[0] = tgsi_build_version();
header = (struct tgsi_header *) &tokens[1];
header = (struct tgsi_header *) &tokens[0];
*header = tgsi_build_header();
*(struct tgsi_processor *) &tokens[2] = tgsi_build_processor(TGSI_PROCESSOR_VERTEX, header);
*(struct tgsi_processor *) &tokens[1] = tgsi_build_processor(TGSI_PROCESSOR_VERTEX, header);
ti = 3;
ti = 2;
/*
* decl i0 ; Vertex pos
@ -185,12 +184,11 @@ create_intra_frag_shader(struct vl_mpeg12_mc_renderer *r)
assert(r);
tokens = (struct tgsi_token *) malloc(max_tokens * sizeof(struct tgsi_token));
*(struct tgsi_version *) &tokens[0] = tgsi_build_version();
header = (struct tgsi_header *) &tokens[1];
header = (struct tgsi_header *) &tokens[0];
*header = tgsi_build_header();
*(struct tgsi_processor *) &tokens[2] = tgsi_build_processor(TGSI_PROCESSOR_FRAGMENT, header);
*(struct tgsi_processor *) &tokens[1] = tgsi_build_processor(TGSI_PROCESSOR_FRAGMENT, header);
ti = 3;
ti = 2;
/*
* decl i0 ; Luma texcoords
@ -237,10 +235,10 @@ create_intra_frag_shader(struct vl_mpeg12_mc_renderer *r)
ti += tgsi_build_full_instruction(&inst, &tokens[ti], header, max_tokens - ti);
inst = vl_inst2(TGSI_OPCODE_MOV, TGSI_FILE_TEMPORARY, 0, TGSI_FILE_TEMPORARY, 1);
inst.FullSrcRegisters[0].SrcRegister.SwizzleX = TGSI_SWIZZLE_X;
inst.FullSrcRegisters[0].SrcRegister.SwizzleY = TGSI_SWIZZLE_X;
inst.FullSrcRegisters[0].SrcRegister.SwizzleZ = TGSI_SWIZZLE_X;
inst.FullDstRegisters[0].DstRegister.WriteMask = TGSI_WRITEMASK_X << i;
inst.Src[0].Register.SwizzleX = TGSI_SWIZZLE_X;
inst.Src[0].Register.SwizzleY = TGSI_SWIZZLE_X;
inst.Src[0].Register.SwizzleZ = TGSI_SWIZZLE_X;
inst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_X << i;
ti += tgsi_build_full_instruction(&inst, &tokens[ti], header, max_tokens - ti);
}
@ -278,12 +276,11 @@ create_frame_pred_vert_shader(struct vl_mpeg12_mc_renderer *r)
assert(r);
tokens = (struct tgsi_token *) malloc(max_tokens * sizeof(struct tgsi_token));
*(struct tgsi_version *) &tokens[0] = tgsi_build_version();
header = (struct tgsi_header *) &tokens[1];
header = (struct tgsi_header *) &tokens[0];
*header = tgsi_build_header();
*(struct tgsi_processor *) &tokens[2] = tgsi_build_processor(TGSI_PROCESSOR_VERTEX, header);
*(struct tgsi_processor *) &tokens[1] = tgsi_build_processor(TGSI_PROCESSOR_VERTEX, header);
ti = 3;
ti = 2;
/*
* decl i0 ; Vertex pos
@ -361,12 +358,11 @@ create_frame_pred_frag_shader(struct vl_mpeg12_mc_renderer *r)
assert(r);
tokens = (struct tgsi_token *) malloc(max_tokens * sizeof(struct tgsi_token));
*(struct tgsi_version *) &tokens[0] = tgsi_build_version();
header = (struct tgsi_header *) &tokens[1];
header = (struct tgsi_header *) &tokens[0];
*header = tgsi_build_header();
*(struct tgsi_processor *) &tokens[2] = tgsi_build_processor(TGSI_PROCESSOR_FRAGMENT, header);
*(struct tgsi_processor *) &tokens[1] = tgsi_build_processor(TGSI_PROCESSOR_FRAGMENT, header);
ti = 3;
ti = 2;
/*
* decl i0 ; Luma texcoords
@ -415,10 +411,10 @@ create_frame_pred_frag_shader(struct vl_mpeg12_mc_renderer *r)
ti += tgsi_build_full_instruction(&inst, &tokens[ti], header, max_tokens - ti);
inst = vl_inst2(TGSI_OPCODE_MOV, TGSI_FILE_TEMPORARY, 0, TGSI_FILE_TEMPORARY, 1);
inst.FullSrcRegisters[0].SrcRegister.SwizzleX = TGSI_SWIZZLE_X;
inst.FullSrcRegisters[0].SrcRegister.SwizzleY = TGSI_SWIZZLE_X;
inst.FullSrcRegisters[0].SrcRegister.SwizzleZ = TGSI_SWIZZLE_X;
inst.FullDstRegisters[0].DstRegister.WriteMask = TGSI_WRITEMASK_X << i;
inst.Src[0].Register.SwizzleX = TGSI_SWIZZLE_X;
inst.Src[0].Register.SwizzleY = TGSI_SWIZZLE_X;
inst.Src[0].Register.SwizzleZ = TGSI_SWIZZLE_X;
inst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_X << i;
ti += tgsi_build_full_instruction(&inst, &tokens[ti], header, max_tokens - ti);
}
@ -470,12 +466,11 @@ create_frame_bi_pred_vert_shader(struct vl_mpeg12_mc_renderer *r)
assert(r);
tokens = (struct tgsi_token *) malloc(max_tokens * sizeof(struct tgsi_token));
*(struct tgsi_version *) &tokens[0] = tgsi_build_version();
header = (struct tgsi_header *) &tokens[1];
header = (struct tgsi_header *) &tokens[0];
*header = tgsi_build_header();
*(struct tgsi_processor *) &tokens[2] = tgsi_build_processor(TGSI_PROCESSOR_VERTEX, header);
*(struct tgsi_processor *) &tokens[1] = tgsi_build_processor(TGSI_PROCESSOR_VERTEX, header);
ti = 3;
ti = 2;
/*
* decl i0 ; Vertex pos
@ -561,12 +556,11 @@ create_frame_bi_pred_frag_shader(struct vl_mpeg12_mc_renderer *r)
assert(r);
tokens = (struct tgsi_token *) malloc(max_tokens * sizeof(struct tgsi_token));
*(struct tgsi_version *) &tokens[0] = tgsi_build_version();
header = (struct tgsi_header *) &tokens[1];
header = (struct tgsi_header *) &tokens[0];
*header = tgsi_build_header();
*(struct tgsi_processor *) &tokens[2] = tgsi_build_processor(TGSI_PROCESSOR_FRAGMENT, header);
*(struct tgsi_processor *) &tokens[1] = tgsi_build_processor(TGSI_PROCESSOR_FRAGMENT, header);
ti = 3;
ti = 2;
/*
* decl i0 ; Luma texcoords
@ -620,10 +614,10 @@ create_frame_bi_pred_frag_shader(struct vl_mpeg12_mc_renderer *r)
ti += tgsi_build_full_instruction(&inst, &tokens[ti], header, max_tokens - ti);
inst = vl_inst2(TGSI_OPCODE_MOV, TGSI_FILE_TEMPORARY, 0, TGSI_FILE_TEMPORARY, 1);
inst.FullSrcRegisters[0].SrcRegister.SwizzleX = TGSI_SWIZZLE_X;
inst.FullSrcRegisters[0].SrcRegister.SwizzleY = TGSI_SWIZZLE_X;
inst.FullSrcRegisters[0].SrcRegister.SwizzleZ = TGSI_SWIZZLE_X;
inst.FullDstRegisters[0].DstRegister.WriteMask = TGSI_WRITEMASK_X << i;
inst.Src[0].Register.SwizzleX = TGSI_SWIZZLE_X;
inst.Src[0].Register.SwizzleY = TGSI_SWIZZLE_X;
inst.Src[0].Register.SwizzleZ = TGSI_SWIZZLE_X;
inst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_X << i;
ti += tgsi_build_full_instruction(&inst, &tokens[ti], header, max_tokens - ti);
}
@ -642,10 +636,10 @@ create_frame_bi_pred_frag_shader(struct vl_mpeg12_mc_renderer *r)
/* lerp t1, c1.x, t1, t2 ; Blend past and future texels */
inst = vl_inst4(TGSI_OPCODE_LRP, TGSI_FILE_TEMPORARY, 1, TGSI_FILE_CONSTANT, 1, TGSI_FILE_TEMPORARY, 1, TGSI_FILE_TEMPORARY, 2);
inst.FullSrcRegisters[0].SrcRegister.SwizzleX = TGSI_SWIZZLE_X;
inst.FullSrcRegisters[0].SrcRegister.SwizzleY = TGSI_SWIZZLE_X;
inst.FullSrcRegisters[0].SrcRegister.SwizzleZ = TGSI_SWIZZLE_X;
inst.FullSrcRegisters[0].SrcRegister.SwizzleW = TGSI_SWIZZLE_X;
inst.Src[0].Register.SwizzleX = TGSI_SWIZZLE_X;
inst.Src[0].Register.SwizzleY = TGSI_SWIZZLE_X;
inst.Src[0].Register.SwizzleZ = TGSI_SWIZZLE_X;
inst.Src[0].Register.SwizzleW = TGSI_SWIZZLE_X;
ti += tgsi_build_full_instruction(&inst, &tokens[ti], header, max_tokens - ti);
/* add o0, t0, t1 ; Add past/future ref and differential to form final output */

91
src/gallium/auxiliary/vl/vl_shader_build.c
View file

@ -36,10 +36,10 @@ struct tgsi_full_declaration vl_decl_input(unsigned int name, unsigned int index
decl.Declaration.File = TGSI_FILE_INPUT;
decl.Declaration.Semantic = 1;
decl.Semantic.SemanticName = name;
decl.Semantic.SemanticIndex = index;
decl.DeclarationRange.First = first;
decl.DeclarationRange.Last = last;
decl.Semantic.Name = name;
decl.Semantic.Index = index;
decl.Range.First = first;
decl.Range.Last = last;
return decl;
}
@ -64,11 +64,11 @@ struct tgsi_full_declaration vl_decl_interpolated_input
decl.Declaration.File = TGSI_FILE_INPUT;
decl.Declaration.Semantic = 1;
decl.Semantic.SemanticName = name;
decl.Semantic.SemanticIndex = index;
decl.Semantic.Name = name;
decl.Semantic.Index = index;
decl.Declaration.Interpolate = interpolation;;
decl.DeclarationRange.First = first;
decl.DeclarationRange.Last = last;
decl.Range.First = first;
decl.Range.Last = last;
return decl;
}
@ -79,10 +79,10 @@ struct tgsi_full_declaration vl_decl_constants(unsigned int name, unsigned int i
decl.Declaration.File = TGSI_FILE_CONSTANT;
decl.Declaration.Semantic = 1;
decl.Semantic.SemanticName = name;
decl.Semantic.SemanticIndex = index;
decl.DeclarationRange.First = first;
decl.DeclarationRange.Last = last;
decl.Semantic.Name = name;
decl.Semantic.Index = index;
decl.Range.First = first;
decl.Range.Last = last;
return decl;
}
@ -93,10 +93,10 @@ struct tgsi_full_declaration vl_decl_output(unsigned int name, unsigned int inde
decl.Declaration.File = TGSI_FILE_OUTPUT;
decl.Declaration.Semantic = 1;
decl.Semantic.SemanticName = name;
decl.Semantic.SemanticIndex = index;
decl.DeclarationRange.First = first;
decl.DeclarationRange.Last = last;
decl.Semantic.Name = name;
decl.Semantic.Index = index;
decl.Range.First = first;
decl.Range.Last = last;
return decl;
}
@ -107,8 +107,8 @@ struct tgsi_full_declaration vl_decl_temps(unsigned int first, unsigned int last
decl = tgsi_default_full_declaration();
decl.Declaration.File = TGSI_FILE_TEMPORARY;
decl.DeclarationRange.First = first;
decl.DeclarationRange.Last = last;
decl.Range.First = first;
decl.Range.Last = last;
return decl;
}
@ -119,8 +119,8 @@ struct tgsi_full_declaration vl_decl_samplers(unsigned int first, unsigned int l
decl = tgsi_default_full_declaration();
decl.Declaration.File = TGSI_FILE_SAMPLER;
decl.DeclarationRange.First = first;
decl.DeclarationRange.Last = last;
decl.Range.First = first;
decl.Range.Last = last;
return decl;
}
@ -138,11 +138,11 @@ struct tgsi_full_instruction vl_inst2
inst.Instruction.Opcode = opcode;
inst.Instruction.NumDstRegs = 1;
inst.FullDstRegisters[0].DstRegister.File = dst_file;
inst.FullDstRegisters[0].DstRegister.Index = dst_index;
inst.Dst[0].Register.File = dst_file;
inst.Dst[0].Register.Index = dst_index;
inst.Instruction.NumSrcRegs = 1;
inst.FullSrcRegisters[0].SrcRegister.File = src_file;
inst.FullSrcRegisters[0].SrcRegister.Index = src_index;
inst.Src[0].Register.File = src_file;
inst.Src[0].Register.Index = src_index;
return inst;
}
@ -162,13 +162,13 @@ struct tgsi_full_instruction vl_inst3
inst.Instruction.Opcode = opcode;
inst.Instruction.NumDstRegs = 1;
inst.FullDstRegisters[0].DstRegister.File = dst_file;
inst.FullDstRegisters[0].DstRegister.Index = dst_index;
inst.Dst[0].Register.File = dst_file;
inst.Dst[0].Register.Index = dst_index;
inst.Instruction.NumSrcRegs = 2;
inst.FullSrcRegisters[0].SrcRegister.File = src1_file;
inst.FullSrcRegisters[0].SrcRegister.Index = src1_index;
inst.FullSrcRegisters[1].SrcRegister.File = src2_file;
inst.FullSrcRegisters[1].SrcRegister.Index = src2_index;
inst.Src[0].Register.File = src1_file;
inst.Src[0].Register.Index = src1_index;
inst.Src[1].Register.File = src2_file;
inst.Src[1].Register.Index = src2_index;
return inst;
}
@ -188,14 +188,15 @@ struct tgsi_full_instruction vl_tex
inst.Instruction.Opcode = TGSI_OPCODE_TEX;
inst.Instruction.NumDstRegs = 1;
inst.FullDstRegisters[0].DstRegister.File = dst_file;
inst.FullDstRegisters[0].DstRegister.Index = dst_index;
inst.Dst[0].Register.File = dst_file;
inst.Dst[0].Register.Index = dst_index;
inst.Instruction.NumSrcRegs = 2;
inst.InstructionExtTexture.Texture = tex;
inst.FullSrcRegisters[0].SrcRegister.File = src1_file;
inst.FullSrcRegisters[0].SrcRegister.Index = src1_index;
inst.FullSrcRegisters[1].SrcRegister.File = src2_file;
inst.FullSrcRegisters[1].SrcRegister.Index = src2_index;
inst.Instruction.Texture = 1;
inst.Texture.Texture = tex;
inst.Src[0].Register.File = src1_file;
inst.Src[0].Register.Index = src1_index;
inst.Src[1].Register.File = src2_file;
inst.Src[1].Register.Index = src2_index;
return inst;
}
@ -217,15 +218,15 @@ struct tgsi_full_instruction vl_inst4
inst.Instruction.Opcode = opcode;
inst.Instruction.NumDstRegs = 1;
inst.FullDstRegisters[0].DstRegister.File = dst_file;
inst.FullDstRegisters[0].DstRegister.Index = dst_index;
inst.Dst[0].Register.File = dst_file;
inst.Dst[0].Register.Index = dst_index;
inst.Instruction.NumSrcRegs = 3;
inst.FullSrcRegisters[0].SrcRegister.File = src1_file;
inst.FullSrcRegisters[0].SrcRegister.Index = src1_index;
inst.FullSrcRegisters[1].SrcRegister.File = src2_file;
inst.FullSrcRegisters[1].SrcRegister.Index = src2_index;
inst.FullSrcRegisters[2].SrcRegister.File = src3_file;
inst.FullSrcRegisters[2].SrcRegister.Index = src3_index;
inst.Src[0].Register.File = src1_file;
inst.Src[0].Register.Index = src1_index;
inst.Src[1].Register.File = src2_file;
inst.Src[1].Register.Index = src2_index;
inst.Src[2].Register.File = src3_file;
inst.Src[2].Register.Index = src3_index;
return inst;
}

252
src/gallium/drivers/cell/ppu/cell_gen_fp.c
View file

@ -237,8 +237,8 @@ is_register_src(struct codegen *gen, int channel,
if (swizzle > TGSI_SWIZZLE_W || sign_op != TGSI_UTIL_SIGN_KEEP) {
return FALSE;
}
if (src->SrcRegister.File == TGSI_FILE_TEMPORARY ||
src->SrcRegister.File == TGSI_FILE_IMMEDIATE) {
if (src->Register.File == TGSI_FILE_TEMPORARY ||
src->Register.File == TGSI_FILE_IMMEDIATE) {
return TRUE;
}
return FALSE;
@ -249,7 +249,7 @@ static boolean
is_memory_dst(struct codegen *gen, int channel,
const struct tgsi_full_dst_register *dst)
{
if (dst->DstRegister.File == TGSI_FILE_OUTPUT) {
if (dst->Register.File == TGSI_FILE_OUTPUT) {
return TRUE;
}
else {
@ -279,15 +279,15 @@ get_src_reg(struct codegen *gen,
assert(swizzle <= TGSI_SWIZZLE_W);
{
int index = src->SrcRegister.Index;
int index = src->Register.Index;
assert(swizzle < 4);
if (src->SrcRegister.Indirect) {
if (src->Register.Indirect) {
/* XXX unfinished */
}
switch (src->SrcRegister.File) {
switch (src->Register.File) {
case TGSI_FILE_TEMPORARY:
reg = gen->temp_regs[index][swizzle];
break;
@ -374,12 +374,12 @@ get_dst_reg(struct codegen *gen,
{
int reg = -1;
switch (dest->DstRegister.File) {
switch (dest->Register.File) {
case TGSI_FILE_TEMPORARY:
if (gen->if_nesting > 0 || gen->loop_nesting > 0)
reg = get_itemp(gen);
else
reg = gen->temp_regs[dest->DstRegister.Index][channel];
reg = gen->temp_regs[dest->Register.Index][channel];
break;
case TGSI_FILE_OUTPUT:
reg = get_itemp(gen);
@ -419,10 +419,10 @@ store_dest_reg(struct codegen *gen,
}
#endif
switch (dest->DstRegister.File) {
switch (dest->Register.File) {
case TGSI_FILE_TEMPORARY:
if (gen->if_nesting > 0 || gen->loop_nesting > 0) {
int d_reg = gen->temp_regs[dest->DstRegister.Index][channel];
int d_reg = gen->temp_regs[dest->Register.Index][channel];
int exec_reg = get_exec_mask_reg(gen);
/* Mix d with new value according to exec mask:
* d[i] = mask_reg[i] ? value_reg : d_reg
@ -437,7 +437,7 @@ store_dest_reg(struct codegen *gen,
case TGSI_FILE_OUTPUT:
{
/* offset is measured in quadwords, not bytes */
int offset = dest->DstRegister.Index * 4 + channel;
int offset = dest->Register.Index * 4 + channel;
if (gen->if_nesting > 0 || gen->loop_nesting > 0) {
int exec_reg = get_exec_mask_reg(gen);
int curval_reg = get_itemp(gen);
@ -544,7 +544,7 @@ emit_epilogue(struct codegen *gen)
#define FOR_EACH_ENABLED_CHANNEL(inst, ch) \
for (ch = 0; ch < 4; ch++) \
if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch))
if (inst->Dst[0].Register.WriteMask & (1 << ch))
static boolean
@ -552,7 +552,7 @@ emit_ARL(struct codegen *gen, const struct tgsi_full_instruction *inst)
{
int ch = 0, src_reg, addr_reg;
src_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
src_reg = get_src_reg(gen, ch, &inst->Src[0]);
addr_reg = get_address_reg(gen);
/* convert float to int */
@ -570,19 +570,19 @@ emit_MOV(struct codegen *gen, const struct tgsi_full_instruction *inst)
int ch, src_reg[4], dst_reg[4];
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
src_reg[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
dst_reg[ch] = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
src_reg[ch] = get_src_reg(gen, ch, &inst->Src[0]);
dst_reg[ch] = get_dst_reg(gen, ch, &inst->Dst[0]);
}
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
if (is_register_src(gen, ch, &inst->FullSrcRegisters[0]) &&
is_memory_dst(gen, ch, &inst->FullDstRegisters[0])) {
if (is_register_src(gen, ch, &inst->Src[0]) &&
is_memory_dst(gen, ch, &inst->Dst[0])) {
/* special-case: register to memory store */
store_dest_reg(gen, src_reg[ch], ch, &inst->FullDstRegisters[0]);
store_dest_reg(gen, src_reg[ch], ch, &inst->Dst[0]);
}
else {
spe_move(gen->f, dst_reg[ch], src_reg[ch]);
store_dest_reg(gen, dst_reg[ch], ch, &inst->FullDstRegisters[0]);
store_dest_reg(gen, dst_reg[ch], ch, &inst->Dst[0]);
}
}
@ -601,9 +601,9 @@ emit_binop(struct codegen *gen, const struct tgsi_full_instruction *inst)
/* Loop over Red/Green/Blue/Alpha channels, fetch src operands */
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
s1_reg[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
s2_reg[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[1]);
d_reg[ch] = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
s1_reg[ch] = get_src_reg(gen, ch, &inst->Src[0]);
s2_reg[ch] = get_src_reg(gen, ch, &inst->Src[1]);
d_reg[ch] = get_dst_reg(gen, ch, &inst->Dst[0]);
}
/* Loop over Red/Green/Blue/Alpha channels, do the op, store results */
@ -626,7 +626,7 @@ emit_binop(struct codegen *gen, const struct tgsi_full_instruction *inst)
/* Store the result (a no-op for TGSI_FILE_TEMPORARY dests) */
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
store_dest_reg(gen, d_reg[ch], ch, &inst->FullDstRegisters[0]);
store_dest_reg(gen, d_reg[ch], ch, &inst->Dst[0]);
}
/* Free any intermediate temps we allocated */
@ -645,16 +645,16 @@ emit_MAD(struct codegen *gen, const struct tgsi_full_instruction *inst)
int ch, s1_reg[4], s2_reg[4], s3_reg[4], d_reg[4];
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
s1_reg[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
s2_reg[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[1]);
s3_reg[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[2]);
d_reg[ch] = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
s1_reg[ch] = get_src_reg(gen, ch, &inst->Src[0]);
s2_reg[ch] = get_src_reg(gen, ch, &inst->Src[1]);
s3_reg[ch] = get_src_reg(gen, ch, &inst->Src[2]);
d_reg[ch] = get_dst_reg(gen, ch, &inst->Dst[0]);
}
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
spe_fma(gen->f, d_reg[ch], s1_reg[ch], s2_reg[ch], s3_reg[ch]);
}
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
store_dest_reg(gen, d_reg[ch], ch, &inst->FullDstRegisters[0]);
store_dest_reg(gen, d_reg[ch], ch, &inst->Dst[0]);
}
free_itemps(gen);
return TRUE;
@ -671,10 +671,10 @@ emit_LRP(struct codegen *gen, const struct tgsi_full_instruction *inst)
/* setup/get src/dst/temp regs */
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
s1_reg[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
s2_reg[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[1]);
s3_reg[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[2]);
d_reg[ch] = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
s1_reg[ch] = get_src_reg(gen, ch, &inst->Src[0]);
s2_reg[ch] = get_src_reg(gen, ch, &inst->Src[1]);
s3_reg[ch] = get_src_reg(gen, ch, &inst->Src[2]);
d_reg[ch] = get_dst_reg(gen, ch, &inst->Dst[0]);
tmp_reg[ch] = get_itemp(gen);
}
@ -687,7 +687,7 @@ emit_LRP(struct codegen *gen, const struct tgsi_full_instruction *inst)
spe_fma(gen->f, d_reg[ch], tmp_reg[ch], s1_reg[ch], s3_reg[ch]);
}
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
store_dest_reg(gen, d_reg[ch], ch, &inst->FullDstRegisters[0]);
store_dest_reg(gen, d_reg[ch], ch, &inst->Dst[0]);
}
free_itemps(gen);
return TRUE;
@ -704,8 +704,8 @@ emit_RCP_RSQ(struct codegen *gen, const struct tgsi_full_instruction *inst)
int ch, s1_reg[4], d_reg[4], tmp_reg[4];
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
s1_reg[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
d_reg[ch] = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
s1_reg[ch] = get_src_reg(gen, ch, &inst->Src[0]);
d_reg[ch] = get_dst_reg(gen, ch, &inst->Dst[0]);
tmp_reg[ch] = get_itemp(gen);
}
@ -726,7 +726,7 @@ emit_RCP_RSQ(struct codegen *gen, const struct tgsi_full_instruction *inst)
}
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
store_dest_reg(gen, d_reg[ch], ch, &inst->FullDstRegisters[0]);
store_dest_reg(gen, d_reg[ch], ch, &inst->Dst[0]);
}
free_itemps(gen);
@ -747,8 +747,8 @@ emit_ABS(struct codegen *gen, const struct tgsi_full_instruction *inst)
spe_load_uint(gen->f, bit31mask_reg, (1 << 31));
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
s1_reg[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
d_reg[ch] = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
s1_reg[ch] = get_src_reg(gen, ch, &inst->Src[0]);
d_reg[ch] = get_dst_reg(gen, ch, &inst->Dst[0]);
}
/* d = sign bit cleared in s1 */
@ -757,7 +757,7 @@ emit_ABS(struct codegen *gen, const struct tgsi_full_instruction *inst)
}
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
store_dest_reg(gen, d_reg[ch], ch, &inst->FullDstRegisters[0]);
store_dest_reg(gen, d_reg[ch], ch, &inst->Dst[0]);
}
free_itemps(gen);
@ -775,12 +775,12 @@ emit_DP3(struct codegen *gen, const struct tgsi_full_instruction *inst)
int s2x_reg, s2y_reg, s2z_reg;
int t0_reg = get_itemp(gen), t1_reg = get_itemp(gen);
s1x_reg = get_src_reg(gen, CHAN_X, &inst->FullSrcRegisters[0]);
s2x_reg = get_src_reg(gen, CHAN_X, &inst->FullSrcRegisters[1]);
s1y_reg = get_src_reg(gen, CHAN_Y, &inst->FullSrcRegisters[0]);
s2y_reg = get_src_reg(gen, CHAN_Y, &inst->FullSrcRegisters[1]);
s1z_reg = get_src_reg(gen, CHAN_Z, &inst->FullSrcRegisters[0]);
s2z_reg = get_src_reg(gen, CHAN_Z, &inst->FullSrcRegisters[1]);
s1x_reg = get_src_reg(gen, CHAN_X, &inst->Src[0]);
s2x_reg = get_src_reg(gen, CHAN_X, &inst->Src[1]);
s1y_reg = get_src_reg(gen, CHAN_Y, &inst->Src[0]);
s2y_reg = get_src_reg(gen, CHAN_Y, &inst->Src[1]);
s1z_reg = get_src_reg(gen, CHAN_Z, &inst->Src[0]);
s2z_reg = get_src_reg(gen, CHAN_Z, &inst->Src[1]);
/* t0 = x0 * x1 */
spe_fm(gen->f, t0_reg, s1x_reg, s2x_reg);
@ -795,9 +795,9 @@ emit_DP3(struct codegen *gen, const struct tgsi_full_instruction *inst)
spe_fa(gen->f, t0_reg, t0_reg, t1_reg);
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
int d_reg = get_dst_reg(gen, ch, &inst->Dst[0]);
spe_move(gen->f, d_reg, t0_reg);
store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
store_dest_reg(gen, d_reg, ch, &inst->Dst[0]);
}
free_itemps(gen);
@ -815,14 +815,14 @@ emit_DP4(struct codegen *gen, const struct tgsi_full_instruction *inst)
int s1x_reg, s1y_reg, s1z_reg, s1w_reg;
int t0_reg = get_itemp(gen), t1_reg = get_itemp(gen);
s0x_reg = get_src_reg(gen, CHAN_X, &inst->FullSrcRegisters[0]);
s1x_reg = get_src_reg(gen, CHAN_X, &inst->FullSrcRegisters[1]);
s0y_reg = get_src_reg(gen, CHAN_Y, &inst->FullSrcRegisters[0]);
s1y_reg = get_src_reg(gen, CHAN_Y, &inst->FullSrcRegisters[1]);
s0z_reg = get_src_reg(gen, CHAN_Z, &inst->FullSrcRegisters[0]);
s1z_reg = get_src_reg(gen, CHAN_Z, &inst->FullSrcRegisters[1]);
s0w_reg = get_src_reg(gen, CHAN_W, &inst->FullSrcRegisters[0]);
s1w_reg = get_src_reg(gen, CHAN_W, &inst->FullSrcRegisters[1]);
s0x_reg = get_src_reg(gen, CHAN_X, &inst->Src[0]);
s1x_reg = get_src_reg(gen, CHAN_X, &inst->Src[1]);
s0y_reg = get_src_reg(gen, CHAN_Y, &inst->Src[0]);
s1y_reg = get_src_reg(gen, CHAN_Y, &inst->Src[1]);
s0z_reg = get_src_reg(gen, CHAN_Z, &inst->Src[0]);
s1z_reg = get_src_reg(gen, CHAN_Z, &inst->Src[1]);
s0w_reg = get_src_reg(gen, CHAN_W, &inst->Src[0]);
s1w_reg = get_src_reg(gen, CHAN_W, &inst->Src[1]);
/* t0 = x0 * x1 */
spe_fm(gen->f, t0_reg, s0x_reg, s1x_reg);
@ -840,9 +840,9 @@ emit_DP4(struct codegen *gen, const struct tgsi_full_instruction *inst)
spe_fa(gen->f, t0_reg, t0_reg, t1_reg);
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
int d_reg = get_dst_reg(gen, ch, &inst->Dst[0]);
spe_move(gen->f, d_reg, t0_reg);
store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
store_dest_reg(gen, d_reg, ch, &inst->Dst[0]);
}
free_itemps(gen);
@ -857,31 +857,31 @@ emit_DPH(struct codegen *gen, const struct tgsi_full_instruction *inst)
{
/* XXX rewrite this function to look more like DP3/DP4 */
int ch;
int s1_reg = get_src_reg(gen, CHAN_X, &inst->FullSrcRegisters[0]);
int s2_reg = get_src_reg(gen, CHAN_X, &inst->FullSrcRegisters[1]);
int s1_reg = get_src_reg(gen, CHAN_X, &inst->Src[0]);
int s2_reg = get_src_reg(gen, CHAN_X, &inst->Src[1]);
int tmp_reg = get_itemp(gen);
/* t = x0 * x1 */
spe_fm(gen->f, tmp_reg, s1_reg, s2_reg);
s1_reg = get_src_reg(gen, CHAN_Y, &inst->FullSrcRegisters[0]);
s2_reg = get_src_reg(gen, CHAN_Y, &inst->FullSrcRegisters[1]);
s1_reg = get_src_reg(gen, CHAN_Y, &inst->Src[0]);
s2_reg = get_src_reg(gen, CHAN_Y, &inst->Src[1]);
/* t = y0 * y1 + t */
spe_fma(gen->f, tmp_reg, s1_reg, s2_reg, tmp_reg);
s1_reg = get_src_reg(gen, CHAN_Z, &inst->FullSrcRegisters[0]);
s2_reg = get_src_reg(gen, CHAN_Z, &inst->FullSrcRegisters[1]);
s1_reg = get_src_reg(gen, CHAN_Z, &inst->Src[0]);
s2_reg = get_src_reg(gen, CHAN_Z, &inst->Src[1]);
/* t = z0 * z1 + t */
spe_fma(gen->f, tmp_reg, s1_reg, s2_reg, tmp_reg);
s2_reg = get_src_reg(gen, CHAN_W, &inst->FullSrcRegisters[1]);
s2_reg = get_src_reg(gen, CHAN_W, &inst->Src[1]);
/* t = w1 + t */
spe_fa(gen->f, tmp_reg, s2_reg, tmp_reg);
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
int d_reg = get_dst_reg(gen, ch, &inst->Dst[0]);
spe_move(gen->f, d_reg, tmp_reg);
store_dest_reg(gen, tmp_reg, ch, &inst->FullDstRegisters[0]);
store_dest_reg(gen, tmp_reg, ch, &inst->Dst[0]);
}
free_itemps(gen);
@ -898,9 +898,9 @@ emit_NRM3(struct codegen *gen, const struct tgsi_full_instruction *inst)
int src_reg[3];
int t0_reg = get_itemp(gen), t1_reg = get_itemp(gen);
src_reg[0] = get_src_reg(gen, CHAN_X, &inst->FullSrcRegisters[0]);
src_reg[1] = get_src_reg(gen, CHAN_Y, &inst->FullSrcRegisters[0]);
src_reg[2] = get_src_reg(gen, CHAN_Z, &inst->FullSrcRegisters[0]);
src_reg[0] = get_src_reg(gen, CHAN_X, &inst->Src[0]);
src_reg[1] = get_src_reg(gen, CHAN_Y, &inst->Src[0]);
src_reg[2] = get_src_reg(gen, CHAN_Z, &inst->Src[0]);
/* t0 = x * x */
spe_fm(gen->f, t0_reg, src_reg[0], src_reg[0]);
@ -919,10 +919,10 @@ emit_NRM3(struct codegen *gen, const struct tgsi_full_instruction *inst)
spe_fi(gen->f, t1_reg, t0_reg, t1_reg);
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
int d_reg = get_dst_reg(gen, ch, &inst->Dst[0]);
/* dst = src[ch] * t1 */
spe_fm(gen->f, d_reg, src_reg[ch], t1_reg);
store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
store_dest_reg(gen, d_reg, ch, &inst->Dst[0]);
}
free_itemps(gen);
@ -936,48 +936,48 @@ emit_NRM3(struct codegen *gen, const struct tgsi_full_instruction *inst)
static boolean
emit_XPD(struct codegen *gen, const struct tgsi_full_instruction *inst)
{
int s1_reg = get_src_reg(gen, CHAN_Z, &inst->FullSrcRegisters[0]);
int s2_reg = get_src_reg(gen, CHAN_Y, &inst->FullSrcRegisters[1]);
int s1_reg = get_src_reg(gen, CHAN_Z, &inst->Src[0]);
int s2_reg = get_src_reg(gen, CHAN_Y, &inst->Src[1]);
int tmp_reg = get_itemp(gen);
/* t = z0 * y1 */
spe_fm(gen->f, tmp_reg, s1_reg, s2_reg);
s1_reg = get_src_reg(gen, CHAN_Y, &inst->FullSrcRegisters[0]);
s2_reg = get_src_reg(gen, CHAN_Z, &inst->FullSrcRegisters[1]);
s1_reg = get_src_reg(gen, CHAN_Y, &inst->Src[0]);
s2_reg = get_src_reg(gen, CHAN_Z, &inst->Src[1]);
/* t = y0 * z1 - t */
spe_fms(gen->f, tmp_reg, s1_reg, s2_reg, tmp_reg);
if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << CHAN_X)) {
store_dest_reg(gen, tmp_reg, CHAN_X, &inst->FullDstRegisters[0]);
if (inst->Dst[0].Register.WriteMask & (1 << CHAN_X)) {
store_dest_reg(gen, tmp_reg, CHAN_X, &inst->Dst[0]);
}
s1_reg = get_src_reg(gen, CHAN_X, &inst->FullSrcRegisters[0]);
s2_reg = get_src_reg(gen, CHAN_Z, &inst->FullSrcRegisters[1]);
s1_reg = get_src_reg(gen, CHAN_X, &inst->Src[0]);
s2_reg = get_src_reg(gen, CHAN_Z, &inst->Src[1]);
/* t = x0 * z1 */
spe_fm(gen->f, tmp_reg, s1_reg, s2_reg);
s1_reg = get_src_reg(gen, CHAN_Z, &inst->FullSrcRegisters[0]);
s2_reg = get_src_reg(gen, CHAN_X, &inst->FullSrcRegisters[1]);
s1_reg = get_src_reg(gen, CHAN_Z, &inst->Src[0]);
s2_reg = get_src_reg(gen, CHAN_X, &inst->Src[1]);
/* t = z0 * x1 - t */
spe_fms(gen->f, tmp_reg, s1_reg, s2_reg, tmp_reg);
if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << CHAN_Y)) {
store_dest_reg(gen, tmp_reg, CHAN_Y, &inst->FullDstRegisters[0]);
if (inst->Dst[0].Register.WriteMask & (1 << CHAN_Y)) {
store_dest_reg(gen, tmp_reg, CHAN_Y, &inst->Dst[0]);
}
s1_reg = get_src_reg(gen, CHAN_Y, &inst->FullSrcRegisters[0]);
s2_reg = get_src_reg(gen, CHAN_X, &inst->FullSrcRegisters[1]);
s1_reg = get_src_reg(gen, CHAN_Y, &inst->Src[0]);
s2_reg = get_src_reg(gen, CHAN_X, &inst->Src[1]);
/* t = y0 * x1 */
spe_fm(gen->f, tmp_reg, s1_reg, s2_reg);
s1_reg = get_src_reg(gen, CHAN_X, &inst->FullSrcRegisters[0]);
s2_reg = get_src_reg(gen, CHAN_Y, &inst->FullSrcRegisters[1]);
s1_reg = get_src_reg(gen, CHAN_X, &inst->Src[0]);
s2_reg = get_src_reg(gen, CHAN_Y, &inst->Src[1]);
/* t = x0 * y1 - t */
spe_fms(gen->f, tmp_reg, s1_reg, s2_reg, tmp_reg);
if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << CHAN_Z)) {
store_dest_reg(gen, tmp_reg, CHAN_Z, &inst->FullDstRegisters[0]);
if (inst->Dst[0].Register.WriteMask & (1 << CHAN_Z)) {
store_dest_reg(gen, tmp_reg, CHAN_Z, &inst->Dst[0]);
}
free_itemps(gen);
@ -1000,9 +1000,9 @@ emit_inequality(struct codegen *gen, const struct tgsi_full_instruction *inst)
one_reg = get_const_one_reg(gen);
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
s1_reg[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
s2_reg[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[1]);
d_reg[ch] = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
s1_reg[ch] = get_src_reg(gen, ch, &inst->Src[0]);
s2_reg[ch] = get_src_reg(gen, ch, &inst->Src[1]);
d_reg[ch] = get_dst_reg(gen, ch, &inst->Dst[0]);
}
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
@ -1043,7 +1043,7 @@ emit_inequality(struct codegen *gen, const struct tgsi_full_instruction *inst)
}
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
store_dest_reg(gen, d_reg[ch], ch, &inst->FullDstRegisters[0]);
store_dest_reg(gen, d_reg[ch], ch, &inst->Dst[0]);
}
free_itemps(gen);
@ -1060,10 +1060,10 @@ emit_CMP(struct codegen *gen, const struct tgsi_full_instruction *inst)
int ch;
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
int s1_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
int s2_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[1]);
int s3_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[2]);
int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
int s1_reg = get_src_reg(gen, ch, &inst->Src[0]);
int s2_reg = get_src_reg(gen, ch, &inst->Src[1]);
int s3_reg = get_src_reg(gen, ch, &inst->Src[2]);
int d_reg = get_dst_reg(gen, ch, &inst->Dst[0]);
int zero_reg = get_itemp(gen);
spe_zero(gen->f, zero_reg);
@ -1072,7 +1072,7 @@ emit_CMP(struct codegen *gen, const struct tgsi_full_instruction *inst)
spe_fcgt(gen->f, d_reg, zero_reg, s1_reg);
spe_selb(gen->f, d_reg, s3_reg, s2_reg, d_reg);
store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
store_dest_reg(gen, d_reg, ch, &inst->Dst[0]);
free_itemps(gen);
}
@ -1090,8 +1090,8 @@ emit_TRUNC(struct codegen *gen, const struct tgsi_full_instruction *inst)
int ch, s1_reg[4], d_reg[4];
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
s1_reg[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
d_reg[ch] = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
s1_reg[ch] = get_src_reg(gen, ch, &inst->Src[0]);
d_reg[ch] = get_dst_reg(gen, ch, &inst->Dst[0]);
}
/* Convert float to int */
@ -1105,7 +1105,7 @@ emit_TRUNC(struct codegen *gen, const struct tgsi_full_instruction *inst)
}
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
store_dest_reg(gen, d_reg[ch], ch, &inst->FullDstRegisters[0]);
store_dest_reg(gen, d_reg[ch], ch, &inst->Dst[0]);
}
free_itemps(gen);
@ -1129,8 +1129,8 @@ emit_FLR(struct codegen *gen, const struct tgsi_full_instruction *inst)
one_reg = get_const_one_reg(gen);
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
s1_reg[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
d_reg[ch] = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
s1_reg[ch] = get_src_reg(gen, ch, &inst->Src[0]);
d_reg[ch] = get_dst_reg(gen, ch, &inst->Dst[0]);
tmp_reg[ch] = get_itemp(gen);
}
@ -1156,7 +1156,7 @@ emit_FLR(struct codegen *gen, const struct tgsi_full_instruction *inst)
}
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
store_dest_reg(gen, d_reg[ch], ch, &inst->FullDstRegisters[0]);
store_dest_reg(gen, d_reg[ch], ch, &inst->Dst[0]);
}
free_itemps(gen);
@ -1177,8 +1177,8 @@ emit_FRC(struct codegen *gen, const struct tgsi_full_instruction *inst)
one_reg = get_const_one_reg(gen);
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
s1_reg[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
d_reg[ch] = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
s1_reg[ch] = get_src_reg(gen, ch, &inst->Src[0]);
d_reg[ch] = get_dst_reg(gen, ch, &inst->Dst[0]);
tmp_reg[ch] = get_itemp(gen);
}
@ -1210,7 +1210,7 @@ emit_FRC(struct codegen *gen, const struct tgsi_full_instruction *inst)
/* store result */
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
store_dest_reg(gen, d_reg[ch], ch, &inst->FullDstRegisters[0]);
store_dest_reg(gen, d_reg[ch], ch, &inst->Dst[0]);
}
free_itemps(gen);
@ -1272,7 +1272,7 @@ emit_function_call(struct codegen *gen,
if (scalar) {
for (a = 0; a < num_args; a++) {
s_regs[a] = get_src_reg(gen, CHAN_X, &inst->FullSrcRegisters[a]);
s_regs[a] = get_src_reg(gen, CHAN_X, &inst->Src[a]);
}
/* we'll call the function, put the return value in this register,
* then replicate it across all write-enabled components in d_reg.
@ -1287,11 +1287,11 @@ emit_function_call(struct codegen *gen,
if (!scalar) {
for (a = 0; a < num_args; a++) {
s_regs[a] = get_src_reg(gen, ch, &inst->FullSrcRegisters[a]);
s_regs[a] = get_src_reg(gen, ch, &inst->Src[a]);
}
}
d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
d_reg = get_dst_reg(gen, ch, &inst->Dst[0]);
if (!scalar || !func_called) {
/* for a scalar function, we'll really only call the function once */
@ -1336,7 +1336,7 @@ emit_function_call(struct codegen *gen,
spe_move(gen->f, d_reg, retval_reg);
}
store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
store_dest_reg(gen, d_reg, ch, &inst->Dst[0]);
free_itemps(gen);
}
@ -1352,7 +1352,7 @@ static boolean
emit_TEX(struct codegen *gen, const struct tgsi_full_instruction *inst)
{
const uint target = inst->InstructionExtTexture.Texture;
const uint unit = inst->FullSrcRegisters[1].SrcRegister.Index;
const uint unit = inst->Src[1].Register.Index;
uint addr;
int ch;
int coord_regs[4], d_regs[4];
@ -1373,14 +1373,14 @@ emit_TEX(struct codegen *gen, const struct tgsi_full_instruction *inst)
return FALSE;
}
assert(inst->FullSrcRegisters[1].SrcRegister.File == TGSI_FILE_SAMPLER);
assert(inst->Src[1].Register.File == TGSI_FILE_SAMPLER);
spe_comment(gen->f, -4, "CALL tex:");
/* get src/dst reg info */
for (ch = 0; ch < 4; ch++) {
coord_regs[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
d_regs[ch] = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
coord_regs[ch] = get_src_reg(gen, ch, &inst->Src[0]);
d_regs[ch] = get_dst_reg(gen, ch, &inst->Dst[0]);
}
{
@ -1425,7 +1425,7 @@ emit_TEX(struct codegen *gen, const struct tgsi_full_instruction *inst)
}
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
store_dest_reg(gen, d_regs[ch], ch, &inst->FullDstRegisters[0]);
store_dest_reg(gen, d_regs[ch], ch, &inst->Dst[0]);
free_itemps(gen);
}
@ -1452,7 +1452,7 @@ emit_KIL(struct codegen *gen, const struct tgsi_full_instruction *inst)
/* get src regs */
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
s_regs[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
s_regs[ch] = get_src_reg(gen, ch, &inst->Src[0]);
}
/* test if any src regs are < 0 */
@ -1500,9 +1500,9 @@ emit_MIN_MAX(struct codegen *gen, const struct tgsi_full_instruction *inst)
int ch, s0_reg[4], s1_reg[4], d_reg[4], tmp_reg[4];
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
s0_reg[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
s1_reg[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[1]);
d_reg[ch] = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
s0_reg[ch] = get_src_reg(gen, ch, &inst->Src[0]);
s1_reg[ch] = get_src_reg(gen, ch, &inst->Src[1]);
d_reg[ch] = get_dst_reg(gen, ch, &inst->Dst[0]);
tmp_reg[ch] = get_itemp(gen);
}
@ -1518,7 +1518,7 @@ emit_MIN_MAX(struct codegen *gen, const struct tgsi_full_instruction *inst)
}
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
store_dest_reg(gen, d_reg[ch], ch, &inst->FullDstRegisters[0]);
store_dest_reg(gen, d_reg[ch], ch, &inst->Dst[0]);
}
free_itemps(gen);
@ -1575,7 +1575,7 @@ emit_IF(struct codegen *gen, const struct tgsi_full_instruction *inst)
/* update conditional execution mask with the predicate register */
int tmp_reg = get_itemp(gen);
int s1_reg = get_src_reg(gen, channel, &inst->FullSrcRegisters[0]);
int s1_reg = get_src_reg(gen, channel, &inst->Src[0]);
/* tmp = (s1_reg == 0) */
spe_ceqi(gen->f, tmp_reg, s1_reg, 0);
@ -1699,8 +1699,8 @@ emit_DDX_DDY(struct codegen *gen, const struct tgsi_full_instruction *inst,
int ch;
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
int s_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
int s_reg = get_src_reg(gen, ch, &inst->Src[0]);
int d_reg = get_dst_reg(gen, ch, &inst->Dst[0]);
int t1_reg = get_itemp(gen);
int t2_reg = get_itemp(gen);
@ -1909,8 +1909,8 @@ emit_declaration(struct cell_context *cell,
switch (decl->Declaration.File) {
case TGSI_FILE_TEMPORARY:
for (i = decl->DeclarationRange.First;
i <= decl->DeclarationRange.Last;
for (i = decl->Range.First;
i <= decl->Range.Last;
i++) {
assert(i < MAX_TEMPS);
for (ch = 0; ch < 4; ch++) {

58
src/gallium/drivers/cell/spu/spu_exec.c
View file

@ -108,10 +108,10 @@
for (CHAN = 0; CHAN < 4; CHAN++)
#define IS_CHANNEL_ENABLED(INST, CHAN)\
((INST).FullDstRegisters[0].DstRegister.WriteMask & (1 << (CHAN)))
((INST).Dst[0].Register.WriteMask & (1 << (CHAN)))
#define IS_CHANNEL_ENABLED2(INST, CHAN)\
((INST).FullDstRegisters[1].DstRegister.WriteMask & (1 << (CHAN)))
((INST).Dst[1].Register.WriteMask & (1 << (CHAN)))
#define FOR_EACH_ENABLED_CHANNEL(INST, CHAN)\
FOR_EACH_CHANNEL( CHAN )\
@ -431,22 +431,22 @@ fetch_source(
index.i[0] =
index.i[1] =
index.i[2] =
index.i[3] = reg->SrcRegister.Index;
index.i[3] = reg->Register.Index;
if (reg->SrcRegister.Indirect) {
if (reg->Register.Indirect) {
union spu_exec_channel index2;
union spu_exec_channel indir_index;
index2.i[0] =
index2.i[1] =
index2.i[2] =
index2.i[3] = reg->SrcRegisterInd.Index;
index2.i[3] = reg->Indirect.Index;
swizzle = tgsi_util_get_src_register_swizzle(&reg->SrcRegisterInd,
swizzle = tgsi_util_get_src_register_swizzle(&reg->Indirect,
CHAN_X);
fetch_src_file_channel(
mach,
reg->SrcRegisterInd.File,
reg->Indirect.File,
swizzle,
&index2,
&indir_index );
@ -454,8 +454,8 @@ fetch_source(
index.q = si_a(index.q, indir_index.q);
}
if( reg->SrcRegister.Dimension ) {
switch( reg->SrcRegister.File ) {
if( reg->Register.Dimension ) {
switch( reg->Register.File ) {
case TGSI_FILE_INPUT:
index.q = si_mpyi(index.q, 17);
break;
@ -466,24 +466,24 @@ fetch_source(
ASSERT( 0 );
}
index.i[0] += reg->SrcRegisterDim.Index;
index.i[1] += reg->SrcRegisterDim.Index;
index.i[2] += reg->SrcRegisterDim.Index;
index.i[3] += reg->SrcRegisterDim.Index;
index.i[0] += reg->Dimension.Index;
index.i[1] += reg->Dimension.Index;
index.i[2] += reg->Dimension.Index;
index.i[3] += reg->Dimension.Index;
if (reg->SrcRegisterDim.Indirect) {
if (reg->Dimension.Indirect) {
union spu_exec_channel index2;
union spu_exec_channel indir_index;
index2.i[0] =
index2.i[1] =
index2.i[2] =
index2.i[3] = reg->SrcRegisterDimInd.Index;
index2.i[3] = reg->DimIndirect.Index;
swizzle = tgsi_util_get_src_register_swizzle( &reg->SrcRegisterDimInd, CHAN_X );
swizzle = tgsi_util_get_src_register_swizzle( &reg->DimIndirect, CHAN_X );
fetch_src_file_channel(
mach,
reg->SrcRegisterDimInd.File,
reg->DimIndirect.File,
swizzle,
&index2,
&indir_index );
@ -495,7 +495,7 @@ fetch_source(
swizzle = tgsi_util_get_full_src_register_swizzle( reg, chan_index );
fetch_src_file_channel(
mach,
reg->SrcRegister.File,
reg->Register.File,
swizzle,
&index,
chan );
@ -517,7 +517,7 @@ fetch_source(
break;
}
if (reg->SrcRegisterExtMod.Complement) {
if (reg->RegisterExtMod.Complement) {
chan->q = si_fs(mach->Temps[TEMP_1_I].xyzw[TEMP_1_C].q, chan->q);
}
}
@ -532,21 +532,21 @@ store_dest(
{
union spu_exec_channel *dst;
switch( reg->DstRegister.File ) {
switch( reg->Register.File ) {
case TGSI_FILE_NULL:
return;
case TGSI_FILE_OUTPUT:
dst = &mach->Outputs[mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
+ reg->DstRegister.Index].xyzw[chan_index];
+ reg->Register.Index].xyzw[chan_index];
break;
case TGSI_FILE_TEMPORARY:
dst = &mach->Temps[reg->DstRegister.Index].xyzw[chan_index];
dst = &mach->Temps[reg->Register.Index].xyzw[chan_index];
break;
case TGSI_FILE_ADDRESS:
dst = &mach->Addrs[reg->DstRegister.Index].xyzw[chan_index];
dst = &mach->Addrs[reg->Register.Index].xyzw[chan_index];
break;
default:
@ -583,10 +583,10 @@ store_dest(
}
#define FETCH(VAL,INDEX,CHAN)\
fetch_source (mach, VAL, &inst->FullSrcRegisters[INDEX], CHAN)
fetch_source (mach, VAL, &inst->Src[INDEX], CHAN)
#define STORE(VAL,INDEX,CHAN)\
store_dest (mach, VAL, &inst->FullDstRegisters[INDEX], inst, CHAN )
store_dest (mach, VAL, &inst->Dst[INDEX], inst, CHAN )
/**
@ -612,7 +612,7 @@ exec_kil(struct spu_exec_machine *mach,
/* unswizzle channel */
swizzle = tgsi_util_get_full_src_register_swizzle (
&inst->FullSrcRegisters[0],
&inst->Src[0],
chan_index);
/* check if the component has not been already tested */
@ -677,7 +677,7 @@ exec_tex(struct spu_exec_machine *mach,
const struct tgsi_full_instruction *inst,
boolean biasLod, boolean projected)
{
const uint unit = inst->FullSrcRegisters[1].SrcRegister.Index;
const uint unit = inst->Src[1].Register.Index;
union spu_exec_channel r[8];
uint chan_index;
float lodBias;
@ -833,8 +833,8 @@ exec_declaration(struct spu_exec_machine *mach,
unsigned first, last, mask;
interpolation_func interp;
first = decl->DeclarationRange.First;
last = decl->DeclarationRange.Last;
first = decl->Range.First;
last = decl->Range.Last;
mask = decl->Declaration.UsageMask;
switch( decl->Declaration.Interpolate ) {

10
src/gallium/drivers/cell/spu/spu_util.c
View file

@ -33,7 +33,7 @@ tgsi_util_get_full_src_register_swizzle(
unsigned component )
{
return tgsi_util_get_src_register_swizzle(
reg->SrcRegister,
reg->Register,
component );
}
@ -45,10 +45,10 @@ tgsi_util_get_full_src_register_sign_mode(
{
unsigned sign_mode;
if( reg->SrcRegisterExtMod.Absolute ) {
if( reg->RegisterExtMod.Absolute ) {
/* Consider only the post-abs negation. */
if( reg->SrcRegisterExtMod.Negate ) {
if( reg->RegisterExtMod.Negate ) {
sign_mode = TGSI_UTIL_SIGN_SET;
}
else {
@ -60,8 +60,8 @@ tgsi_util_get_full_src_register_sign_mode(
unsigned negate;
negate = reg->SrcRegister.Negate;
if( reg->SrcRegisterExtMod.Negate ) {
negate = reg->Register.Negate;
if( reg->RegisterExtMod.Negate ) {
negate = !negate;
}

151
src/gallium/drivers/i915/i915_fpc_translate.c
View file

@ -143,12 +143,12 @@ static uint
src_vector(struct i915_fp_compile *p,
const struct tgsi_full_src_register *source)
{
uint index = source->SrcRegister.Index;
uint index = source->Register.Index;
uint src = 0, sem_name, sem_ind;
switch (source->SrcRegister.File) {
switch (source->Register.File) {
case TGSI_FILE_TEMPORARY:
if (source->SrcRegister.Index >= I915_MAX_TEMPORARY) {
if (source->Register.Index >= I915_MAX_TEMPORARY) {
i915_program_error(p, "Exceeded max temporary reg");
return 0;
}
@ -215,26 +215,25 @@ src_vector(struct i915_fp_compile *p,
}
src = swizzle(src,
source->SrcRegister.SwizzleX,
source->SrcRegister.SwizzleY,
source->SrcRegister.SwizzleZ,
source->SrcRegister.SwizzleW);
source->Register.SwizzleX,
source->Register.SwizzleY,
source->Register.SwizzleZ,
source->Register.SwizzleW);
/* There's both negate-all-components and per-component negation.
* Try to handle both here.
*/
{
int n = source->SrcRegister.Negate;
int n = source->Register.Negate;
src = negate(src, n, n, n, n);
}
/* no abs() or post-abs negation */
/* no abs() */
#if 0
/* XXX assertions disabled to allow arbfplight.c to run */
/* XXX enable these assertions, or fix things */
assert(!source->SrcRegisterExtMod.Absolute);
assert(!source->SrcRegisterExtMod.Negate);
assert(!source->Register.Absolute);
#endif
return src;
}
@ -247,10 +246,10 @@ static uint
get_result_vector(struct i915_fp_compile *p,
const struct tgsi_full_dst_register *dest)
{
switch (dest->DstRegister.File) {
switch (dest->Register.File) {
case TGSI_FILE_OUTPUT:
{
uint sem_name = p->shader->info.output_semantic_name[dest->DstRegister.Index];
uint sem_name = p->shader->info.output_semantic_name[dest->Register.Index];
switch (sem_name) {
case TGSI_SEMANTIC_POSITION:
return UREG(REG_TYPE_OD, 0);
@ -262,7 +261,7 @@ get_result_vector(struct i915_fp_compile *p,
}
}
case TGSI_FILE_TEMPORARY:
return UREG(REG_TYPE_R, dest->DstRegister.Index);
return UREG(REG_TYPE_R, dest->Register.Index);
default:
i915_program_error(p, "Bad inst->DstReg.File");
return 0;
@ -277,7 +276,7 @@ static uint
get_result_flags(const struct tgsi_full_instruction *inst)
{
const uint writeMask
= inst->FullDstRegisters[0].DstRegister.WriteMask;
= inst->Dst[0].Register.WriteMask;
uint flags = 0x0;
if (inst->Instruction.Saturate == TGSI_SAT_ZERO_ONE)
@ -339,14 +338,14 @@ emit_tex(struct i915_fp_compile *p,
const struct tgsi_full_instruction *inst,
uint opcode)
{
uint texture = inst->InstructionExtTexture.Texture;
uint unit = inst->FullSrcRegisters[1].SrcRegister.Index;
uint texture = inst->Texture.Texture;
uint unit = inst->Src[1].Register.Index;
uint tex = translate_tex_src_target( p, texture );
uint sampler = i915_emit_decl(p, REG_TYPE_S, unit, tex);
uint coord = src_vector( p, &inst->FullSrcRegisters[0]);
uint coord = src_vector( p, &inst->Src[0]);
i915_emit_texld( p,
get_result_vector( p, &inst->FullDstRegisters[0] ),
get_result_vector( p, &inst->Dst[0] ),
get_result_flags( inst ),
sampler,
coord,
@ -368,13 +367,13 @@ emit_simple_arith(struct i915_fp_compile *p,
assert(numArgs <= 3);
arg1 = (numArgs < 1) ? 0 : src_vector( p, &inst->FullSrcRegisters[0] );
arg2 = (numArgs < 2) ? 0 : src_vector( p, &inst->FullSrcRegisters[1] );
arg3 = (numArgs < 3) ? 0 : src_vector( p, &inst->FullSrcRegisters[2] );
arg1 = (numArgs < 1) ? 0 : src_vector( p, &inst->Src[0] );
arg2 = (numArgs < 2) ? 0 : src_vector( p, &inst->Src[1] );
arg3 = (numArgs < 3) ? 0 : src_vector( p, &inst->Src[2] );
i915_emit_arith( p,
opcode,
get_result_vector( p, &inst->FullDstRegisters[0]),
get_result_vector( p, &inst->Dst[0]),
get_result_flags( inst ), 0,
arg1,
arg2,
@ -394,8 +393,8 @@ emit_simple_arith_swap2(struct i915_fp_compile *p,
/* transpose first two registers */
inst2 = *inst;
inst2.FullSrcRegisters[0] = inst->FullSrcRegisters[1];
inst2.FullSrcRegisters[1] = inst->FullSrcRegisters[0];
inst2.Src[0] = inst->Src[1];
inst2.Src[1] = inst->Src[0];
emit_simple_arith(p, &inst2, opcode, numArgs);
}
@ -424,10 +423,10 @@ i915_translate_instruction(struct i915_fp_compile *p,
switch (inst->Instruction.Opcode) {
case TGSI_OPCODE_ABS:
src0 = src_vector(p, &inst->FullSrcRegisters[0]);
src0 = src_vector(p, &inst->Src[0]);
i915_emit_arith(p,
A0_MAX,
get_result_vector(p, &inst->FullDstRegisters[0]),
get_result_vector(p, &inst->Dst[0]),
get_result_flags(inst), 0,
src0, negate(src0, 1, 1, 1, 1), 0);
break;
@ -437,17 +436,17 @@ i915_translate_instruction(struct i915_fp_compile *p,
break;
case TGSI_OPCODE_CMP:
src0 = src_vector(p, &inst->FullSrcRegisters[0]);
src1 = src_vector(p, &inst->FullSrcRegisters[1]);
src2 = src_vector(p, &inst->FullSrcRegisters[2]);
src0 = src_vector(p, &inst->Src[0]);
src1 = src_vector(p, &inst->Src[1]);
src2 = src_vector(p, &inst->Src[2]);
i915_emit_arith(p, A0_CMP,
get_result_vector(p, &inst->FullDstRegisters[0]),
get_result_vector(p, &inst->Dst[0]),
get_result_flags(inst),
0, src0, src2, src1); /* NOTE: order of src2, src1 */
break;
case TGSI_OPCODE_COS:
src0 = src_vector(p, &inst->FullSrcRegisters[0]);
src0 = src_vector(p, &inst->Src[0]);
tmp = i915_get_utemp(p);
i915_emit_arith(p,
@ -490,7 +489,7 @@ i915_translate_instruction(struct i915_fp_compile *p,
i915_emit_arith(p,
A0_DP4,
get_result_vector(p, &inst->FullDstRegisters[0]),
get_result_vector(p, &inst->Dst[0]),
get_result_flags(inst), 0,
swizzle(tmp, ONE, Z, Y, X),
i915_emit_const4fv(p, cos_constants), 0);
@ -505,19 +504,19 @@ i915_translate_instruction(struct i915_fp_compile *p,
break;
case TGSI_OPCODE_DPH:
src0 = src_vector(p, &inst->FullSrcRegisters[0]);
src1 = src_vector(p, &inst->FullSrcRegisters[1]);
src0 = src_vector(p, &inst->Src[0]);
src1 = src_vector(p, &inst->Src[1]);
i915_emit_arith(p,
A0_DP4,
get_result_vector(p, &inst->FullDstRegisters[0]),
get_result_vector(p, &inst->Dst[0]),
get_result_flags(inst), 0,
swizzle(src0, X, Y, Z, ONE), src1, 0);
break;
case TGSI_OPCODE_DST:
src0 = src_vector(p, &inst->FullSrcRegisters[0]);
src1 = src_vector(p, &inst->FullSrcRegisters[1]);
src0 = src_vector(p, &inst->Src[0]);
src1 = src_vector(p, &inst->Src[1]);
/* result[0] = 1 * 1;
* result[1] = a[1] * b[1];
@ -526,7 +525,7 @@ i915_translate_instruction(struct i915_fp_compile *p,
*/
i915_emit_arith(p,
A0_MUL,
get_result_vector(p, &inst->FullDstRegisters[0]),
get_result_vector(p, &inst->Dst[0]),
get_result_flags(inst), 0,
swizzle(src0, ONE, Y, Z, ONE),
swizzle(src1, ONE, Y, ONE, W), 0);
@ -537,11 +536,11 @@ i915_translate_instruction(struct i915_fp_compile *p,
break;
case TGSI_OPCODE_EX2:
src0 = src_vector(p, &inst->FullSrcRegisters[0]);
src0 = src_vector(p, &inst->Src[0]);
i915_emit_arith(p,
A0_EXP,
get_result_vector(p, &inst->FullDstRegisters[0]),
get_result_vector(p, &inst->Dst[0]),
get_result_flags(inst), 0,
swizzle(src0, X, X, X, X), 0, 0);
break;
@ -556,7 +555,7 @@ i915_translate_instruction(struct i915_fp_compile *p,
case TGSI_OPCODE_KIL:
/* kill if src[0].x < 0 || src[0].y < 0 ... */
src0 = src_vector(p, &inst->FullSrcRegisters[0]);
src0 = src_vector(p, &inst->Src[0]);
tmp = i915_get_utemp(p);
i915_emit_texld(p,
@ -572,17 +571,17 @@ i915_translate_instruction(struct i915_fp_compile *p,
break;
case TGSI_OPCODE_LG2:
src0 = src_vector(p, &inst->FullSrcRegisters[0]);
src0 = src_vector(p, &inst->Src[0]);
i915_emit_arith(p,
A0_LOG,
get_result_vector(p, &inst->FullDstRegisters[0]),
get_result_vector(p, &inst->Dst[0]),
get_result_flags(inst), 0,
swizzle(src0, X, X, X, X), 0, 0);
break;
case TGSI_OPCODE_LIT:
src0 = src_vector(p, &inst->FullSrcRegisters[0]);
src0 = src_vector(p, &inst->Src[0]);
tmp = i915_get_utemp(p);
/* tmp = max( a.xyzw, a.00zw )
@ -606,7 +605,7 @@ i915_translate_instruction(struct i915_fp_compile *p,
swizzle(tmp, Y, Y, Y, Y), 0, 0);
i915_emit_arith(p, A0_CMP,
get_result_vector(p, &inst->FullDstRegisters[0]),
get_result_vector(p, &inst->Dst[0]),
get_result_flags(inst), 0,
negate(swizzle(tmp, ONE, ONE, X, ONE), 0, 0, 1, 0),
swizzle(tmp, ONE, X, ZERO, ONE),
@ -615,9 +614,9 @@ i915_translate_instruction(struct i915_fp_compile *p,
break;
case TGSI_OPCODE_LRP:
src0 = src_vector(p, &inst->FullSrcRegisters[0]);
src1 = src_vector(p, &inst->FullSrcRegisters[1]);
src2 = src_vector(p, &inst->FullSrcRegisters[2]);
src0 = src_vector(p, &inst->Src[0]);
src1 = src_vector(p, &inst->Src[1]);
src2 = src_vector(p, &inst->Src[2]);
flags = get_result_flags(inst);
tmp = i915_get_utemp(p);
@ -632,7 +631,7 @@ i915_translate_instruction(struct i915_fp_compile *p,
flags & A0_DEST_CHANNEL_ALL, 0, src1, src0, src2);
i915_emit_arith(p, A0_MAD,
get_result_vector(p, &inst->FullDstRegisters[0]),
get_result_vector(p, &inst->Dst[0]),
flags, 0, negate(src2, 1, 1, 1, 1), src0, tmp);
break;
@ -645,8 +644,8 @@ i915_translate_instruction(struct i915_fp_compile *p,
break;
case TGSI_OPCODE_MIN:
src0 = src_vector(p, &inst->FullSrcRegisters[0]);
src1 = src_vector(p, &inst->FullSrcRegisters[1]);
src0 = src_vector(p, &inst->Src[0]);
src1 = src_vector(p, &inst->Src[1]);
tmp = i915_get_utemp(p);
flags = get_result_flags(inst);
@ -658,7 +657,7 @@ i915_translate_instruction(struct i915_fp_compile *p,
i915_emit_arith(p,
A0_MOV,
get_result_vector(p, &inst->FullDstRegisters[0]),
get_result_vector(p, &inst->Dst[0]),
flags, 0, negate(tmp, 1, 1, 1, 1), 0, 0);
break;
@ -671,8 +670,8 @@ i915_translate_instruction(struct i915_fp_compile *p,
break;
case TGSI_OPCODE_POW:
src0 = src_vector(p, &inst->FullSrcRegisters[0]);
src1 = src_vector(p, &inst->FullSrcRegisters[1]);
src0 = src_vector(p, &inst->Src[0]);
src1 = src_vector(p, &inst->Src[1]);
tmp = i915_get_utemp(p);
flags = get_result_flags(inst);
@ -687,7 +686,7 @@ i915_translate_instruction(struct i915_fp_compile *p,
i915_emit_arith(p,
A0_EXP,
get_result_vector(p, &inst->FullDstRegisters[0]),
get_result_vector(p, &inst->Dst[0]),
flags, 0, swizzle(tmp, X, X, X, X), 0, 0);
break;
@ -696,27 +695,27 @@ i915_translate_instruction(struct i915_fp_compile *p,
break;
case TGSI_OPCODE_RCP:
src0 = src_vector(p, &inst->FullSrcRegisters[0]);
src0 = src_vector(p, &inst->Src[0]);
i915_emit_arith(p,
A0_RCP,
get_result_vector(p, &inst->FullDstRegisters[0]),
get_result_vector(p, &inst->Dst[0]),
get_result_flags(inst), 0,
swizzle(src0, X, X, X, X), 0, 0);
break;
case TGSI_OPCODE_RSQ:
src0 = src_vector(p, &inst->FullSrcRegisters[0]);
src0 = src_vector(p, &inst->Src[0]);
i915_emit_arith(p,
A0_RSQ,
get_result_vector(p, &inst->FullDstRegisters[0]),
get_result_vector(p, &inst->Dst[0]),
get_result_flags(inst), 0,
swizzle(src0, X, X, X, X), 0, 0);
break;
case TGSI_OPCODE_SCS:
src0 = src_vector(p, &inst->FullSrcRegisters[0]);
src0 = src_vector(p, &inst->Src[0]);
tmp = i915_get_utemp(p);
/*
@ -739,7 +738,7 @@ i915_translate_instruction(struct i915_fp_compile *p,
swizzle(tmp, X, Y, X, Y),
swizzle(tmp, X, X, ONE, ONE), 0);
writemask = inst->FullDstRegisters[0].DstRegister.WriteMask;
writemask = inst->Dst[0].Register.WriteMask;
if (writemask & TGSI_WRITEMASK_Y) {
uint tmp1;
@ -757,7 +756,7 @@ i915_translate_instruction(struct i915_fp_compile *p,
i915_emit_arith(p,
A0_DP4,
get_result_vector(p, &inst->FullDstRegisters[0]),
get_result_vector(p, &inst->Dst[0]),
A0_DEST_CHANNEL_Y, 0,
swizzle(tmp1, W, Z, Y, X),
i915_emit_const4fv(p, sin_constants), 0);
@ -772,7 +771,7 @@ i915_translate_instruction(struct i915_fp_compile *p,
i915_emit_arith(p,
A0_DP4,
get_result_vector(p, &inst->FullDstRegisters[0]),
get_result_vector(p, &inst->Dst[0]),
A0_DEST_CHANNEL_X, 0,
swizzle(tmp, ONE, Z, Y, X),
i915_emit_const4fv(p, cos_constants), 0);
@ -789,7 +788,7 @@ i915_translate_instruction(struct i915_fp_compile *p,
break;
case TGSI_OPCODE_SIN:
src0 = src_vector(p, &inst->FullSrcRegisters[0]);
src0 = src_vector(p, &inst->Src[0]);
tmp = i915_get_utemp(p);
i915_emit_arith(p,
@ -832,7 +831,7 @@ i915_translate_instruction(struct i915_fp_compile *p,
i915_emit_arith(p,
A0_DP4,
get_result_vector(p, &inst->FullDstRegisters[0]),
get_result_vector(p, &inst->Dst[0]),
get_result_flags(inst), 0,
swizzle(tmp, W, Z, Y, X),
i915_emit_const4fv(p, sin_constants), 0);
@ -848,12 +847,12 @@ i915_translate_instruction(struct i915_fp_compile *p,
break;
case TGSI_OPCODE_SUB:
src0 = src_vector(p, &inst->FullSrcRegisters[0]);
src1 = src_vector(p, &inst->FullSrcRegisters[1]);
src0 = src_vector(p, &inst->Src[0]);
src1 = src_vector(p, &inst->Src[1]);
i915_emit_arith(p,
A0_ADD,
get_result_vector(p, &inst->FullDstRegisters[0]),
get_result_vector(p, &inst->Dst[0]),
get_result_flags(inst), 0,
src0, negate(src1, 1, 1, 1, 1), 0);
break;
@ -877,8 +876,8 @@ i915_translate_instruction(struct i915_fp_compile *p,
* result.z = src0.x * src1.y - src0.y * src1.x;
* result.w = undef;
*/
src0 = src_vector(p, &inst->FullSrcRegisters[0]);
src1 = src_vector(p, &inst->FullSrcRegisters[1]);
src0 = src_vector(p, &inst->Src[0]);
src1 = src_vector(p, &inst->Src[1]);
tmp = i915_get_utemp(p);
i915_emit_arith(p,
@ -889,7 +888,7 @@ i915_translate_instruction(struct i915_fp_compile *p,
i915_emit_arith(p,
A0_MAD,
get_result_vector(p, &inst->FullDstRegisters[0]),
get_result_vector(p, &inst->Dst[0]),
get_result_flags(inst), 0,
swizzle(src0, Y, Z, X, ONE),
swizzle(src1, Z, X, Y, ONE),
@ -929,8 +928,8 @@ i915_translate_instructions(struct i915_fp_compile *p,
if (parse.FullToken.FullDeclaration.Declaration.File
== TGSI_FILE_CONSTANT) {
uint i;
for (i = parse.FullToken.FullDeclaration.DeclarationRange.First;
i <= parse.FullToken.FullDeclaration.DeclarationRange.Last;
for (i = parse.FullToken.FullDeclaration.Range.First;
i <= parse.FullToken.FullDeclaration.Range.Last;
i++) {
assert(ifs->constant_flags[i] == 0x0);
ifs->constant_flags[i] = I915_CONSTFLAG_USER;
@ -940,8 +939,8 @@ i915_translate_instructions(struct i915_fp_compile *p,
else if (parse.FullToken.FullDeclaration.Declaration.File
== TGSI_FILE_TEMPORARY) {
uint i;
for (i = parse.FullToken.FullDeclaration.DeclarationRange.First;
i <= parse.FullToken.FullDeclaration.DeclarationRange.Last;
for (i = parse.FullToken.FullDeclaration.Range.First;
i <= parse.FullToken.FullDeclaration.Range.Last;
i++) {
assert(i < I915_MAX_TEMPORARY);
/* XXX just use shader->info->file_mask[TGSI_FILE_TEMPORARY] */

4
src/gallium/drivers/llvmpipe/lp_bld_interp.c
View file

@ -303,8 +303,8 @@ lp_build_interp_soa_init(struct lp_build_interp_soa_context *bld,
unsigned first, last, mask;
unsigned attrib;
first = decl->DeclarationRange.First;
last = decl->DeclarationRange.Last;
first = decl->Range.First;
last = decl->Range.Last;
mask = decl->Declaration.UsageMask;
for( attrib = first; attrib <= last; ++attrib ) {

40
src/gallium/drivers/llvmpipe/lp_bld_tgsi_soa.c
View file

@ -64,7 +64,7 @@
for (CHAN = 0; CHAN < NUM_CHANNELS; CHAN++)
#define IS_DST0_CHANNEL_ENABLED( INST, CHAN )\
((INST)->FullDstRegisters[0].DstRegister.WriteMask & (1 << (CHAN)))
((INST)->Dst[0].Register.WriteMask & (1 << (CHAN)))
#define IF_IS_DST0_CHANNEL_ENABLED( INST, CHAN )\
if (IS_DST0_CHANNEL_ENABLED( INST, CHAN ))
@ -157,7 +157,7 @@ emit_fetch(
unsigned index,
const unsigned chan_index )
{
const struct tgsi_full_src_register *reg = &inst->FullSrcRegisters[index];
const struct tgsi_full_src_register *reg = &inst->Src[index];
unsigned swizzle = tgsi_util_get_full_src_register_swizzle( reg, chan_index );
LLVMValueRef res;
@ -167,9 +167,9 @@ emit_fetch(
case TGSI_SWIZZLE_Z:
case TGSI_SWIZZLE_W:
switch (reg->SrcRegister.File) {
switch (reg->Register.File) {
case TGSI_FILE_CONSTANT: {
LLVMValueRef index = LLVMConstInt(LLVMInt32Type(), reg->SrcRegister.Index*4 + swizzle, 0);
LLVMValueRef index = LLVMConstInt(LLVMInt32Type(), reg->Register.Index*4 + swizzle, 0);
LLVMValueRef scalar_ptr = LLVMBuildGEP(bld->base.builder, bld->consts_ptr, &index, 1, "");
LLVMValueRef scalar = LLVMBuildLoad(bld->base.builder, scalar_ptr, "");
res = lp_build_broadcast_scalar(&bld->base, scalar);
@ -177,17 +177,17 @@ emit_fetch(
}
case TGSI_FILE_IMMEDIATE:
res = bld->immediates[reg->SrcRegister.Index][swizzle];
res = bld->immediates[reg->Register.Index][swizzle];
assert(res);
break;
case TGSI_FILE_INPUT:
res = bld->inputs[reg->SrcRegister.Index][swizzle];
res = bld->inputs[reg->Register.Index][swizzle];
assert(res);
break;
case TGSI_FILE_TEMPORARY:
res = bld->temps[reg->SrcRegister.Index][swizzle];
res = bld->temps[reg->Register.Index][swizzle];
if(!res)
return bld->base.undef;
break;
@ -267,7 +267,7 @@ emit_store(
unsigned chan_index,
LLVMValueRef value)
{
const struct tgsi_full_dst_register *reg = &inst->FullDstRegisters[index];
const struct tgsi_full_dst_register *reg = &inst->Dst[index];
switch( inst->Instruction.Saturate ) {
case TGSI_SAT_NONE:
@ -287,13 +287,13 @@ emit_store(
assert(0);
}
switch( reg->DstRegister.File ) {
switch( reg->Register.File ) {
case TGSI_FILE_OUTPUT:
bld->outputs[reg->DstRegister.Index][chan_index] = value;
bld->outputs[reg->Register.Index][chan_index] = value;
break;
case TGSI_FILE_TEMPORARY:
bld->temps[reg->DstRegister.Index][chan_index] = value;
bld->temps[reg->Register.Index][chan_index] = value;
break;
case TGSI_FILE_ADDRESS:
@ -319,14 +319,14 @@ emit_tex( struct lp_build_tgsi_soa_context *bld,
boolean projected,
LLVMValueRef *texel)
{
const uint unit = inst->FullSrcRegisters[1].SrcRegister.Index;
const uint unit = inst->Src[1].Register.Index;
LLVMValueRef lodbias;
LLVMValueRef oow;
LLVMValueRef coords[3];
unsigned num_coords;
unsigned i;
switch (inst->InstructionExtTexture.Texture) {
switch (inst->Texture.Texture) {
case TGSI_TEXTURE_1D:
num_coords = 1;
break;
@ -375,7 +375,7 @@ emit_kil(
struct lp_build_tgsi_soa_context *bld,
const struct tgsi_full_instruction *inst )
{
const struct tgsi_full_src_register *reg = &inst->FullSrcRegisters[0];
const struct tgsi_full_src_register *reg = &inst->Src[0];
LLVMValueRef terms[NUM_CHANNELS];
LLVMValueRef mask;
unsigned chan_index;
@ -423,15 +423,15 @@ indirect_temp_reference(const struct tgsi_full_instruction *inst)
{
uint i;
for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
const struct tgsi_full_src_register *reg = &inst->FullSrcRegisters[i];
if (reg->SrcRegister.File == TGSI_FILE_TEMPORARY &&
reg->SrcRegister.Indirect)
const struct tgsi_full_src_register *reg = &inst->Src[i];
if (reg->Register.File == TGSI_FILE_TEMPORARY &&
reg->Register.Indirect)
return TRUE;
}
for (i = 0; i < inst->Instruction.NumDstRegs; i++) {
const struct tgsi_full_dst_register *reg = &inst->FullDstRegisters[i];
if (reg->DstRegister.File == TGSI_FILE_TEMPORARY &&
reg->DstRegister.Indirect)
const struct tgsi_full_dst_register *reg = &inst->Dst[i];
if (reg->Register.File == TGSI_FILE_TEMPORARY &&
reg->Register.Indirect)
return TRUE;
}
return FALSE;

68
src/gallium/drivers/nv20/nv20_vertprog.c
View file

@ -253,32 +253,32 @@ static INLINE struct nv20_sreg
tgsi_src(struct nv20_vpc *vpc, const struct tgsi_full_src_register *fsrc) {
struct nv20_sreg src;
switch (fsrc->SrcRegister.File) {
switch (fsrc->Register.File) {
case TGSI_FILE_INPUT:
src = nv20_sr(NV30SR_INPUT, fsrc->SrcRegister.Index);
src = nv20_sr(NV30SR_INPUT, fsrc->Register.Index);
break;
case TGSI_FILE_CONSTANT:
src = constant(vpc, fsrc->SrcRegister.Index, 0, 0, 0, 0);
src = constant(vpc, fsrc->Register.Index, 0, 0, 0, 0);
break;
case TGSI_FILE_IMMEDIATE:
src = vpc->imm[fsrc->SrcRegister.Index];
src = vpc->imm[fsrc->Register.Index];
break;
case TGSI_FILE_TEMPORARY:
if (vpc->high_temp < fsrc->SrcRegister.Index)
vpc->high_temp = fsrc->SrcRegister.Index;
src = nv20_sr(NV30SR_TEMP, fsrc->SrcRegister.Index);
if (vpc->high_temp < fsrc->Register.Index)
vpc->high_temp = fsrc->Register.Index;
src = nv20_sr(NV30SR_TEMP, fsrc->Register.Index);
break;
default:
NOUVEAU_ERR("bad src file\n");
break;
}
src.abs = fsrc->SrcRegisterExtMod.Absolute;
src.negate = fsrc->SrcRegister.Negate;
src.swz[0] = fsrc->SrcRegister.SwizzleX;
src.swz[1] = fsrc->SrcRegister.SwizzleY;
src.swz[2] = fsrc->SrcRegister.SwizzleZ;
src.swz[3] = fsrc->SrcRegister.SwizzleW;
src.abs = fsrc->Register.Absolute;
src.negate = fsrc->Register.Negate;
src.swz[0] = fsrc->Register.SwizzleX;
src.swz[1] = fsrc->Register.SwizzleY;
src.swz[2] = fsrc->Register.SwizzleZ;
src.swz[3] = fsrc->Register.SwizzleW;
return src;
}
@ -286,14 +286,14 @@ static INLINE struct nv20_sreg
tgsi_dst(struct nv20_vpc *vpc, const struct tgsi_full_dst_register *fdst) {
struct nv20_sreg dst;
switch (fdst->DstRegister.File) {
switch (fdst->Register.File) {
case TGSI_FILE_OUTPUT:
dst = nv20_sr(NV30SR_OUTPUT,
vpc->output_map[fdst->DstRegister.Index]);
vpc->output_map[fdst->Register.Index]);
break;
case TGSI_FILE_TEMPORARY:
dst = nv20_sr(NV30SR_TEMP, fdst->DstRegister.Index);
dst = nv20_sr(NV30SR_TEMP, fdst->Register.Index);
if (vpc->high_temp < dst.index)
vpc->high_temp = dst.index;
break;
@ -334,8 +334,8 @@ nv20_vertprog_parse_instruction(struct nv20_vpc *vpc,
for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
const struct tgsi_full_src_register *fsrc;
fsrc = &finst->FullSrcRegisters[i];
if (fsrc->SrcRegister.File == TGSI_FILE_TEMPORARY) {
fsrc = &finst->Src[i];
if (fsrc->Register.File == TGSI_FILE_TEMPORARY) {
src[i] = tgsi_src(vpc, fsrc);
}
}
@ -343,11 +343,11 @@ nv20_vertprog_parse_instruction(struct nv20_vpc *vpc,
for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
const struct tgsi_full_src_register *fsrc;
fsrc = &finst->FullSrcRegisters[i];
switch (fsrc->SrcRegister.File) {
fsrc = &finst->Src[i];
switch (fsrc->Register.File) {
case TGSI_FILE_INPUT:
if (ai == -1 || ai == fsrc->SrcRegister.Index) {
ai = fsrc->SrcRegister.Index;
if (ai == -1 || ai == fsrc->Register.Index) {
ai = fsrc->Register.Index;
src[i] = tgsi_src(vpc, fsrc);
} else {
src[i] = temp(vpc);
@ -360,8 +360,8 @@ nv20_vertprog_parse_instruction(struct nv20_vpc *vpc,
*/
case TGSI_FILE_CONSTANT:
case TGSI_FILE_IMMEDIATE:
if (ci == -1 || ci == fsrc->SrcRegister.Index) {
ci = fsrc->SrcRegister.Index;
if (ci == -1 || ci == fsrc->Register.Index) {
ci = fsrc->Register.Index;
src[i] = tgsi_src(vpc, fsrc);
} else {
src[i] = temp(vpc);
@ -378,8 +378,8 @@ nv20_vertprog_parse_instruction(struct nv20_vpc *vpc,
}
}
dst = tgsi_dst(vpc, &finst->FullDstRegisters[0]);
mask = tgsi_mask(finst->FullDstRegisters[0].DstRegister.WriteMask);
dst = tgsi_dst(vpc, &finst->Dst[0]);
mask = tgsi_mask(finst->Dst[0].Register.WriteMask);
switch (finst->Instruction.Opcode) {
case TGSI_OPCODE_ABS:
@ -490,15 +490,15 @@ nv20_vertprog_parse_decl_output(struct nv20_vpc *vpc,
{
int hw;
switch (fdec->Semantic.SemanticName) {
switch (fdec->Semantic.Name) {
case TGSI_SEMANTIC_POSITION:
hw = NV30_VP_INST_DEST_POS;
break;
case TGSI_SEMANTIC_COLOR:
if (fdec->Semantic.SemanticIndex == 0) {
if (fdec->Semantic.Index == 0) {
hw = NV30_VP_INST_DEST_COL0;
} else
if (fdec->Semantic.SemanticIndex == 1) {
if (fdec->Semantic.Index == 1) {
hw = NV30_VP_INST_DEST_COL1;
} else {
NOUVEAU_ERR("bad colour semantic index\n");
@ -506,10 +506,10 @@ nv20_vertprog_parse_decl_output(struct nv20_vpc *vpc,
}
break;
case TGSI_SEMANTIC_BCOLOR:
if (fdec->Semantic.SemanticIndex == 0) {
if (fdec->Semantic.Index == 0) {
hw = NV30_VP_INST_DEST_BFC0;
} else
if (fdec->Semantic.SemanticIndex == 1) {
if (fdec->Semantic.Index == 1) {
hw = NV30_VP_INST_DEST_BFC1;
} else {
NOUVEAU_ERR("bad bcolour semantic index\n");
@ -523,8 +523,8 @@ nv20_vertprog_parse_decl_output(struct nv20_vpc *vpc,
hw = NV30_VP_INST_DEST_PSZ;
break;
case TGSI_SEMANTIC_GENERIC:
if (fdec->Semantic.SemanticIndex <= 7) {
hw = NV30_VP_INST_DEST_TC(fdec->Semantic.SemanticIndex);
if (fdec->Semantic.Index <= 7) {
hw = NV30_VP_INST_DEST_TC(fdec->Semantic.Index);
} else {
NOUVEAU_ERR("bad generic semantic index\n");
return FALSE;
@ -535,7 +535,7 @@ nv20_vertprog_parse_decl_output(struct nv20_vpc *vpc,
return FALSE;
}
vpc->output_map[fdec->DeclarationRange.First] = hw;
vpc->output_map[fdec->Range.First] = hw;
return TRUE;
}

82
src/gallium/drivers/nv30/nv30_fragprog.c
View file

@ -237,20 +237,20 @@ tgsi_src(struct nv30_fpc *fpc, const struct tgsi_full_src_register *fsrc)
{
struct nv30_sreg src;
switch (fsrc->SrcRegister.File) {
switch (fsrc->Register.File) {
case TGSI_FILE_INPUT:
src = nv30_sr(NV30SR_INPUT,
fpc->attrib_map[fsrc->SrcRegister.Index]);
fpc->attrib_map[fsrc->Register.Index]);
break;
case TGSI_FILE_CONSTANT:
src = constant(fpc, fsrc->SrcRegister.Index, NULL);
src = constant(fpc, fsrc->Register.Index, NULL);
break;
case TGSI_FILE_IMMEDIATE:
assert(fsrc->SrcRegister.Index < fpc->nr_imm);
src = fpc->imm[fsrc->SrcRegister.Index];
assert(fsrc->Register.Index < fpc->nr_imm);
src = fpc->imm[fsrc->Register.Index];
break;
case TGSI_FILE_TEMPORARY:
src = nv30_sr(NV30SR_TEMP, fsrc->SrcRegister.Index + 1);
src = nv30_sr(NV30SR_TEMP, fsrc->Register.Index + 1);
if (fpc->high_temp < src.index)
fpc->high_temp = src.index;
break;
@ -258,7 +258,7 @@ tgsi_src(struct nv30_fpc *fpc, const struct tgsi_full_src_register *fsrc)
* Luckily fragprog results are just temp regs..
*/
case TGSI_FILE_OUTPUT:
if (fsrc->SrcRegister.Index == fpc->colour_id)
if (fsrc->Register.Index == fpc->colour_id)
return nv30_sr(NV30SR_OUTPUT, 0);
else
return nv30_sr(NV30SR_OUTPUT, 1);
@ -268,12 +268,12 @@ tgsi_src(struct nv30_fpc *fpc, const struct tgsi_full_src_register *fsrc)
break;
}
src.abs = fsrc->SrcRegisterExtMod.Absolute;
src.negate = fsrc->SrcRegister.Negate;
src.swz[0] = fsrc->SrcRegister.SwizzleX;
src.swz[1] = fsrc->SrcRegister.SwizzleY;
src.swz[2] = fsrc->SrcRegister.SwizzleZ;
src.swz[3] = fsrc->SrcRegister.SwizzleW;
src.abs = fsrc->Register.Absolute;
src.negate = fsrc->Register.Negate;
src.swz[0] = fsrc->Register.SwizzleX;
src.swz[1] = fsrc->Register.SwizzleY;
src.swz[2] = fsrc->Register.SwizzleZ;
src.swz[3] = fsrc->Register.SwizzleW;
return src;
}
@ -281,22 +281,22 @@ static INLINE struct nv30_sreg
tgsi_dst(struct nv30_fpc *fpc, const struct tgsi_full_dst_register *fdst) {
int idx;
switch (fdst->DstRegister.File) {
switch (fdst->Register.File) {
case TGSI_FILE_OUTPUT:
if (fdst->DstRegister.Index == fpc->colour_id)
if (fdst->Register.Index == fpc->colour_id)
return nv30_sr(NV30SR_OUTPUT, 0);
else
return nv30_sr(NV30SR_OUTPUT, 1);
break;
case TGSI_FILE_TEMPORARY:
idx = fdst->DstRegister.Index + 1;
idx = fdst->Register.Index + 1;
if (fpc->high_temp < idx)
fpc->high_temp = idx;
return nv30_sr(NV30SR_TEMP, idx);
case TGSI_FILE_NULL:
return nv30_sr(NV30SR_NONE, 0);
default:
NOUVEAU_ERR("bad dst file %d\n", fdst->DstRegister.File);
NOUVEAU_ERR("bad dst file %d\n", fdst->Register.File);
return nv30_sr(NV30SR_NONE, 0);
}
}
@ -363,8 +363,8 @@ nv30_fragprog_parse_instruction(struct nv30_fpc *fpc,
for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
const struct tgsi_full_src_register *fsrc;
fsrc = &finst->FullSrcRegisters[i];
if (fsrc->SrcRegister.File == TGSI_FILE_TEMPORARY) {
fsrc = &finst->Src[i];
if (fsrc->Register.File == TGSI_FILE_TEMPORARY) {
src[i] = tgsi_src(fpc, fsrc);
}
}
@ -372,9 +372,9 @@ nv30_fragprog_parse_instruction(struct nv30_fpc *fpc,
for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
const struct tgsi_full_src_register *fsrc;
fsrc = &finst->FullSrcRegisters[i];
fsrc = &finst->Src[i];
switch (fsrc->SrcRegister.File) {
switch (fsrc->Register.File) {
case TGSI_FILE_INPUT:
case TGSI_FILE_CONSTANT:
case TGSI_FILE_TEMPORARY:
@ -385,14 +385,14 @@ nv30_fragprog_parse_instruction(struct nv30_fpc *fpc,
break;
}
switch (fsrc->SrcRegister.File) {
switch (fsrc->Register.File) {
case TGSI_FILE_INPUT:
if (ai == -1 || ai == fsrc->SrcRegister.Index) {
ai = fsrc->SrcRegister.Index;
if (ai == -1 || ai == fsrc->Register.Index) {
ai = fsrc->Register.Index;
src[i] = tgsi_src(fpc, fsrc);
} else {
NOUVEAU_MSG("extra src attr %d\n",
fsrc->SrcRegister.Index);
fsrc->Register.Index);
src[i] = temp(fpc);
arith(fpc, 0, MOV, src[i], MASK_ALL,
tgsi_src(fpc, fsrc), none, none);
@ -400,8 +400,8 @@ nv30_fragprog_parse_instruction(struct nv30_fpc *fpc,
break;
case TGSI_FILE_CONSTANT:
case TGSI_FILE_IMMEDIATE:
if (ci == -1 || ci == fsrc->SrcRegister.Index) {
ci = fsrc->SrcRegister.Index;
if (ci == -1 || ci == fsrc->Register.Index) {
ci = fsrc->Register.Index;
src[i] = tgsi_src(fpc, fsrc);
} else {
src[i] = temp(fpc);
@ -413,7 +413,7 @@ nv30_fragprog_parse_instruction(struct nv30_fpc *fpc,
/* handled above */
break;
case TGSI_FILE_SAMPLER:
unit = fsrc->SrcRegister.Index;
unit = fsrc->Register.Index;
break;
case TGSI_FILE_OUTPUT:
break;
@ -423,8 +423,8 @@ nv30_fragprog_parse_instruction(struct nv30_fpc *fpc,
}
}
dst = tgsi_dst(fpc, &finst->FullDstRegisters[0]);
mask = tgsi_mask(finst->FullDstRegisters[0].DstRegister.WriteMask);
dst = tgsi_dst(fpc, &finst->Dst[0]);
mask = tgsi_mask(finst->Dst[0].Register.WriteMask);
sat = (finst->Instruction.Saturate == TGSI_SAT_ZERO_ONE);
switch (finst->Instruction.Opcode) {
@ -572,15 +572,15 @@ nv30_fragprog_parse_decl_attrib(struct nv30_fpc *fpc,
{
int hw;
switch (fdec->Semantic.SemanticName) {
switch (fdec->Semantic.Name) {
case TGSI_SEMANTIC_POSITION:
hw = NV30_FP_OP_INPUT_SRC_POSITION;
break;
case TGSI_SEMANTIC_COLOR:
if (fdec->Semantic.SemanticIndex == 0) {
if (fdec->Semantic.Index == 0) {
hw = NV30_FP_OP_INPUT_SRC_COL0;
} else
if (fdec->Semantic.SemanticIndex == 1) {
if (fdec->Semantic.Index == 1) {
hw = NV30_FP_OP_INPUT_SRC_COL1;
} else {
NOUVEAU_ERR("bad colour semantic index\n");
@ -591,9 +591,9 @@ nv30_fragprog_parse_decl_attrib(struct nv30_fpc *fpc,
hw = NV30_FP_OP_INPUT_SRC_FOGC;
break;
case TGSI_SEMANTIC_GENERIC:
if (fdec->Semantic.SemanticIndex <= 7) {
if (fdec->Semantic.Index <= 7) {
hw = NV30_FP_OP_INPUT_SRC_TC(fdec->Semantic.
SemanticIndex);
Index);
} else {
NOUVEAU_ERR("bad generic semantic index\n");
return FALSE;
@ -604,7 +604,7 @@ nv30_fragprog_parse_decl_attrib(struct nv30_fpc *fpc,
return FALSE;
}
fpc->attrib_map[fdec->DeclarationRange.First] = hw;
fpc->attrib_map[fdec->Range.First] = hw;
return TRUE;
}
@ -612,12 +612,12 @@ static boolean
nv30_fragprog_parse_decl_output(struct nv30_fpc *fpc,
const struct tgsi_full_declaration *fdec)
{
switch (fdec->Semantic.SemanticName) {
switch (fdec->Semantic.Name) {
case TGSI_SEMANTIC_POSITION:
fpc->depth_id = fdec->DeclarationRange.First;
fpc->depth_id = fdec->Range.First;
break;
case TGSI_SEMANTIC_COLOR:
fpc->colour_id = fdec->DeclarationRange.First;
fpc->colour_id = fdec->Range.First;
break;
default:
NOUVEAU_ERR("bad output semantic\n");
@ -653,9 +653,9 @@ nv30_fragprog_prepare(struct nv30_fpc *fpc)
goto out_err;
break;
/*case TGSI_FILE_TEMPORARY:
if (fdec->DeclarationRange.Last > high_temp) {
if (fdec->Range.Last > high_temp) {
high_temp =
fdec->DeclarationRange.Last;
fdec->Range.Last;
}
break;*/
default:

68
src/gallium/drivers/nv30/nv30_vertprog.c
View file

@ -253,32 +253,32 @@ static INLINE struct nv30_sreg
tgsi_src(struct nv30_vpc *vpc, const struct tgsi_full_src_register *fsrc) {
struct nv30_sreg src;
switch (fsrc->SrcRegister.File) {
switch (fsrc->Register.File) {
case TGSI_FILE_INPUT:
src = nv30_sr(NV30SR_INPUT, fsrc->SrcRegister.Index);
src = nv30_sr(NV30SR_INPUT, fsrc->Register.Index);
break;
case TGSI_FILE_CONSTANT:
src = constant(vpc, fsrc->SrcRegister.Index, 0, 0, 0, 0);
src = constant(vpc, fsrc->Register.Index, 0, 0, 0, 0);
break;
case TGSI_FILE_IMMEDIATE:
src = vpc->imm[fsrc->SrcRegister.Index];
src = vpc->imm[fsrc->Register.Index];
break;
case TGSI_FILE_TEMPORARY:
if (vpc->high_temp < fsrc->SrcRegister.Index)
vpc->high_temp = fsrc->SrcRegister.Index;
src = nv30_sr(NV30SR_TEMP, fsrc->SrcRegister.Index);
if (vpc->high_temp < fsrc->Register.Index)
vpc->high_temp = fsrc->Register.Index;
src = nv30_sr(NV30SR_TEMP, fsrc->Register.Index);
break;
default:
NOUVEAU_ERR("bad src file\n");
break;
}
src.abs = fsrc->SrcRegisterExtMod.Absolute;
src.negate = fsrc->SrcRegister.Negate;
src.swz[0] = fsrc->SrcRegister.SwizzleX;
src.swz[1] = fsrc->SrcRegister.SwizzleY;
src.swz[2] = fsrc->SrcRegister.SwizzleZ;
src.swz[3] = fsrc->SrcRegister.SwizzleW;
src.abs = fsrc->Register.Absolute;
src.negate = fsrc->Register.Negate;
src.swz[0] = fsrc->Register.SwizzleX;
src.swz[1] = fsrc->Register.SwizzleY;
src.swz[2] = fsrc->Register.SwizzleZ;
src.swz[3] = fsrc->Register.SwizzleW;
return src;
}
@ -286,14 +286,14 @@ static INLINE struct nv30_sreg
tgsi_dst(struct nv30_vpc *vpc, const struct tgsi_full_dst_register *fdst) {
struct nv30_sreg dst;
switch (fdst->DstRegister.File) {
switch (fdst->Register.File) {
case TGSI_FILE_OUTPUT:
dst = nv30_sr(NV30SR_OUTPUT,
vpc->output_map[fdst->DstRegister.Index]);
vpc->output_map[fdst->Register.Index]);
break;
case TGSI_FILE_TEMPORARY:
dst = nv30_sr(NV30SR_TEMP, fdst->DstRegister.Index);
dst = nv30_sr(NV30SR_TEMP, fdst->Register.Index);
if (vpc->high_temp < dst.index)
vpc->high_temp = dst.index;
break;
@ -334,8 +334,8 @@ nv30_vertprog_parse_instruction(struct nv30_vpc *vpc,
for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
const struct tgsi_full_src_register *fsrc;
fsrc = &finst->FullSrcRegisters[i];
if (fsrc->SrcRegister.File == TGSI_FILE_TEMPORARY) {
fsrc = &finst->Src[i];
if (fsrc->Register.File == TGSI_FILE_TEMPORARY) {
src[i] = tgsi_src(vpc, fsrc);
}
}
@ -343,11 +343,11 @@ nv30_vertprog_parse_instruction(struct nv30_vpc *vpc,
for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
const struct tgsi_full_src_register *fsrc;
fsrc = &finst->FullSrcRegisters[i];
switch (fsrc->SrcRegister.File) {
fsrc = &finst->Src[i];
switch (fsrc->Register.File) {
case TGSI_FILE_INPUT:
if (ai == -1 || ai == fsrc->SrcRegister.Index) {
ai = fsrc->SrcRegister.Index;
if (ai == -1 || ai == fsrc->Register.Index) {
ai = fsrc->Register.Index;
src[i] = tgsi_src(vpc, fsrc);
} else {
src[i] = temp(vpc);
@ -360,8 +360,8 @@ nv30_vertprog_parse_instruction(struct nv30_vpc *vpc,
*/
case TGSI_FILE_CONSTANT:
case TGSI_FILE_IMMEDIATE:
if (ci == -1 || ci == fsrc->SrcRegister.Index) {
ci = fsrc->SrcRegister.Index;
if (ci == -1 || ci == fsrc->Register.Index) {
ci = fsrc->Register.Index;
src[i] = tgsi_src(vpc, fsrc);
} else {
src[i] = temp(vpc);
@ -378,8 +378,8 @@ nv30_vertprog_parse_instruction(struct nv30_vpc *vpc,
}
}
dst = tgsi_dst(vpc, &finst->FullDstRegisters[0]);
mask = tgsi_mask(finst->FullDstRegisters[0].DstRegister.WriteMask);
dst = tgsi_dst(vpc, &finst->Dst[0]);
mask = tgsi_mask(finst->Dst[0].Register.WriteMask);
switch (finst->Instruction.Opcode) {
case TGSI_OPCODE_ABS:
@ -490,15 +490,15 @@ nv30_vertprog_parse_decl_output(struct nv30_vpc *vpc,
{
int hw;
switch (fdec->Semantic.SemanticName) {
switch (fdec->Semantic.Name) {
case TGSI_SEMANTIC_POSITION:
hw = NV30_VP_INST_DEST_POS;
break;
case TGSI_SEMANTIC_COLOR:
if (fdec->Semantic.SemanticIndex == 0) {
if (fdec->Semantic.Index == 0) {
hw = NV30_VP_INST_DEST_COL0;
} else
if (fdec->Semantic.SemanticIndex == 1) {
if (fdec->Semantic.Index == 1) {
hw = NV30_VP_INST_DEST_COL1;
} else {
NOUVEAU_ERR("bad colour semantic index\n");
@ -506,10 +506,10 @@ nv30_vertprog_parse_decl_output(struct nv30_vpc *vpc,
}
break;
case TGSI_SEMANTIC_BCOLOR:
if (fdec->Semantic.SemanticIndex == 0) {
if (fdec->Semantic.Index == 0) {
hw = NV30_VP_INST_DEST_BFC0;
} else
if (fdec->Semantic.SemanticIndex == 1) {
if (fdec->Semantic.Index == 1) {
hw = NV30_VP_INST_DEST_BFC1;
} else {
NOUVEAU_ERR("bad bcolour semantic index\n");
@ -523,8 +523,8 @@ nv30_vertprog_parse_decl_output(struct nv30_vpc *vpc,
hw = NV30_VP_INST_DEST_PSZ;
break;
case TGSI_SEMANTIC_GENERIC:
if (fdec->Semantic.SemanticIndex <= 7) {
hw = NV30_VP_INST_DEST_TC(fdec->Semantic.SemanticIndex);
if (fdec->Semantic.Index <= 7) {
hw = NV30_VP_INST_DEST_TC(fdec->Semantic.Index);
} else {
NOUVEAU_ERR("bad generic semantic index\n");
return FALSE;
@ -535,7 +535,7 @@ nv30_vertprog_parse_decl_output(struct nv30_vpc *vpc,
return FALSE;
}
vpc->output_map[fdec->DeclarationRange.First] = hw;
vpc->output_map[fdec->Range.First] = hw;
return TRUE;
}

84
src/gallium/drivers/nv40/nv40_fragprog.c
View file

@ -255,50 +255,50 @@ tgsi_src(struct nv40_fpc *fpc, const struct tgsi_full_src_register *fsrc)
{
struct nv40_sreg src;
switch (fsrc->SrcRegister.File) {
switch (fsrc->Register.File) {
case TGSI_FILE_INPUT:
src = nv40_sr(NV40SR_INPUT,
fpc->attrib_map[fsrc->SrcRegister.Index]);
fpc->attrib_map[fsrc->Register.Index]);
break;
case TGSI_FILE_CONSTANT:
src = constant(fpc, fsrc->SrcRegister.Index, NULL);
src = constant(fpc, fsrc->Register.Index, NULL);
break;
case TGSI_FILE_IMMEDIATE:
assert(fsrc->SrcRegister.Index < fpc->nr_imm);
src = fpc->imm[fsrc->SrcRegister.Index];
assert(fsrc->Register.Index < fpc->nr_imm);
src = fpc->imm[fsrc->Register.Index];
break;
case TGSI_FILE_TEMPORARY:
src = fpc->r_temp[fsrc->SrcRegister.Index];
src = fpc->r_temp[fsrc->Register.Index];
break;
/* NV40 fragprog result regs are just temps, so this is simple */
case TGSI_FILE_OUTPUT:
src = fpc->r_result[fsrc->SrcRegister.Index];
src = fpc->r_result[fsrc->Register.Index];
break;
default:
NOUVEAU_ERR("bad src file\n");
break;
}
src.abs = fsrc->SrcRegisterExtMod.Absolute;
src.negate = fsrc->SrcRegister.Negate;
src.swz[0] = fsrc->SrcRegister.SwizzleX;
src.swz[1] = fsrc->SrcRegister.SwizzleY;
src.swz[2] = fsrc->SrcRegister.SwizzleZ;
src.swz[3] = fsrc->SrcRegister.SwizzleW;
src.abs = fsrc->Register.Absolute;
src.negate = fsrc->Register.Negate;
src.swz[0] = fsrc->Register.SwizzleX;
src.swz[1] = fsrc->Register.SwizzleY;
src.swz[2] = fsrc->Register.SwizzleZ;
src.swz[3] = fsrc->Register.SwizzleW;
return src;
}
static INLINE struct nv40_sreg
tgsi_dst(struct nv40_fpc *fpc, const struct tgsi_full_dst_register *fdst) {
switch (fdst->DstRegister.File) {
switch (fdst->Register.File) {
case TGSI_FILE_OUTPUT:
return fpc->r_result[fdst->DstRegister.Index];
return fpc->r_result[fdst->Register.Index];
case TGSI_FILE_TEMPORARY:
return fpc->r_temp[fdst->DstRegister.Index];
return fpc->r_temp[fdst->Register.Index];
case TGSI_FILE_NULL:
return nv40_sr(NV40SR_NONE, 0);
default:
NOUVEAU_ERR("bad dst file %d\n", fdst->DstRegister.File);
NOUVEAU_ERR("bad dst file %d\n", fdst->Register.File);
return nv40_sr(NV40SR_NONE, 0);
}
}
@ -364,8 +364,8 @@ nv40_fragprog_parse_instruction(struct nv40_fpc *fpc,
for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
const struct tgsi_full_src_register *fsrc;
fsrc = &finst->FullSrcRegisters[i];
if (fsrc->SrcRegister.File == TGSI_FILE_TEMPORARY) {
fsrc = &finst->Src[i];
if (fsrc->Register.File == TGSI_FILE_TEMPORARY) {
src[i] = tgsi_src(fpc, fsrc);
}
}
@ -373,9 +373,9 @@ nv40_fragprog_parse_instruction(struct nv40_fpc *fpc,
for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
const struct tgsi_full_src_register *fsrc;
fsrc = &finst->FullSrcRegisters[i];
fsrc = &finst->Src[i];
switch (fsrc->SrcRegister.File) {
switch (fsrc->Register.File) {
case TGSI_FILE_INPUT:
case TGSI_FILE_CONSTANT:
case TGSI_FILE_TEMPORARY:
@ -386,10 +386,10 @@ nv40_fragprog_parse_instruction(struct nv40_fpc *fpc,
break;
}
switch (fsrc->SrcRegister.File) {
switch (fsrc->Register.File) {
case TGSI_FILE_INPUT:
if (ai == -1 || ai == fsrc->SrcRegister.Index) {
ai = fsrc->SrcRegister.Index;
if (ai == -1 || ai == fsrc->Register.Index) {
ai = fsrc->Register.Index;
src[i] = tgsi_src(fpc, fsrc);
} else {
src[i] = temp(fpc);
@ -399,8 +399,8 @@ nv40_fragprog_parse_instruction(struct nv40_fpc *fpc,
break;
case TGSI_FILE_CONSTANT:
if ((ci == -1 && ii == -1) ||
ci == fsrc->SrcRegister.Index) {
ci = fsrc->SrcRegister.Index;
ci == fsrc->Register.Index) {
ci = fsrc->Register.Index;
src[i] = tgsi_src(fpc, fsrc);
} else {
src[i] = temp(fpc);
@ -410,8 +410,8 @@ nv40_fragprog_parse_instruction(struct nv40_fpc *fpc,
break;
case TGSI_FILE_IMMEDIATE:
if ((ci == -1 && ii == -1) ||
ii == fsrc->SrcRegister.Index) {
ii = fsrc->SrcRegister.Index;
ii == fsrc->Register.Index) {
ii = fsrc->Register.Index;
src[i] = tgsi_src(fpc, fsrc);
} else {
src[i] = temp(fpc);
@ -423,7 +423,7 @@ nv40_fragprog_parse_instruction(struct nv40_fpc *fpc,
/* handled above */
break;
case TGSI_FILE_SAMPLER:
unit = fsrc->SrcRegister.Index;
unit = fsrc->Register.Index;
break;
case TGSI_FILE_OUTPUT:
break;
@ -433,8 +433,8 @@ nv40_fragprog_parse_instruction(struct nv40_fpc *fpc,
}
}
dst = tgsi_dst(fpc, &finst->FullDstRegisters[0]);
mask = tgsi_mask(finst->FullDstRegisters[0].DstRegister.WriteMask);
dst = tgsi_dst(fpc, &finst->Dst[0]);
mask = tgsi_mask(finst->Dst[0].Register.WriteMask);
sat = (finst->Instruction.Saturate == TGSI_SAT_ZERO_ONE);
switch (finst->Instruction.Opcode) {
@ -644,15 +644,15 @@ nv40_fragprog_parse_decl_attrib(struct nv40_fpc *fpc,
{
int hw;
switch (fdec->Semantic.SemanticName) {
switch (fdec->Semantic.Name) {
case TGSI_SEMANTIC_POSITION:
hw = NV40_FP_OP_INPUT_SRC_POSITION;
break;
case TGSI_SEMANTIC_COLOR:
if (fdec->Semantic.SemanticIndex == 0) {
if (fdec->Semantic.Index == 0) {
hw = NV40_FP_OP_INPUT_SRC_COL0;
} else
if (fdec->Semantic.SemanticIndex == 1) {
if (fdec->Semantic.Index == 1) {
hw = NV40_FP_OP_INPUT_SRC_COL1;
} else {
NOUVEAU_ERR("bad colour semantic index\n");
@ -663,9 +663,9 @@ nv40_fragprog_parse_decl_attrib(struct nv40_fpc *fpc,
hw = NV40_FP_OP_INPUT_SRC_FOGC;
break;
case TGSI_SEMANTIC_GENERIC:
if (fdec->Semantic.SemanticIndex <= 7) {
if (fdec->Semantic.Index <= 7) {
hw = NV40_FP_OP_INPUT_SRC_TC(fdec->Semantic.
SemanticIndex);
Index);
} else {
NOUVEAU_ERR("bad generic semantic index\n");
return FALSE;
@ -676,7 +676,7 @@ nv40_fragprog_parse_decl_attrib(struct nv40_fpc *fpc,
return FALSE;
}
fpc->attrib_map[fdec->DeclarationRange.First] = hw;
fpc->attrib_map[fdec->Range.First] = hw;
return TRUE;
}
@ -684,15 +684,15 @@ static boolean
nv40_fragprog_parse_decl_output(struct nv40_fpc *fpc,
const struct tgsi_full_declaration *fdec)
{
unsigned idx = fdec->DeclarationRange.First;
unsigned idx = fdec->Range.First;
unsigned hw;
switch (fdec->Semantic.SemanticName) {
switch (fdec->Semantic.Name) {
case TGSI_SEMANTIC_POSITION:
hw = 1;
break;
case TGSI_SEMANTIC_COLOR:
switch (fdec->Semantic.SemanticIndex) {
switch (fdec->Semantic.Index) {
case 0: hw = 0; break;
case 1: hw = 2; break;
case 2: hw = 3; break;
@ -738,9 +738,9 @@ nv40_fragprog_prepare(struct nv40_fpc *fpc)
goto out_err;
break;
case TGSI_FILE_TEMPORARY:
if (fdec->DeclarationRange.Last > high_temp) {
if (fdec->Range.Last > high_temp) {
high_temp =
fdec->DeclarationRange.Last;
fdec->Range.Last;
}
break;
default:

88
src/gallium/drivers/nv40/nv40_vertprog.c
View file

@ -295,30 +295,30 @@ static INLINE struct nv40_sreg
tgsi_src(struct nv40_vpc *vpc, const struct tgsi_full_src_register *fsrc) {
struct nv40_sreg src;
switch (fsrc->SrcRegister.File) {
switch (fsrc->Register.File) {
case TGSI_FILE_INPUT:
src = nv40_sr(NV40SR_INPUT, fsrc->SrcRegister.Index);
src = nv40_sr(NV40SR_INPUT, fsrc->Register.Index);
break;
case TGSI_FILE_CONSTANT:
src = constant(vpc, fsrc->SrcRegister.Index, 0, 0, 0, 0);
src = constant(vpc, fsrc->Register.Index, 0, 0, 0, 0);
break;
case TGSI_FILE_IMMEDIATE:
src = vpc->imm[fsrc->SrcRegister.Index];
src = vpc->imm[fsrc->Register.Index];
break;
case TGSI_FILE_TEMPORARY:
src = vpc->r_temp[fsrc->SrcRegister.Index];
src = vpc->r_temp[fsrc->Register.Index];
break;
default:
NOUVEAU_ERR("bad src file\n");
break;
}
src.abs = fsrc->SrcRegisterExtMod.Absolute;
src.negate = fsrc->SrcRegister.Negate;
src.swz[0] = fsrc->SrcRegister.SwizzleX;
src.swz[1] = fsrc->SrcRegister.SwizzleY;
src.swz[2] = fsrc->SrcRegister.SwizzleZ;
src.swz[3] = fsrc->SrcRegister.SwizzleW;
src.abs = fsrc->Register.Absolute;
src.negate = fsrc->Register.Negate;
src.swz[0] = fsrc->Register.SwizzleX;
src.swz[1] = fsrc->Register.SwizzleY;
src.swz[2] = fsrc->Register.SwizzleZ;
src.swz[3] = fsrc->Register.SwizzleW;
return src;
}
@ -326,15 +326,15 @@ static INLINE struct nv40_sreg
tgsi_dst(struct nv40_vpc *vpc, const struct tgsi_full_dst_register *fdst) {
struct nv40_sreg dst;
switch (fdst->DstRegister.File) {
switch (fdst->Register.File) {
case TGSI_FILE_OUTPUT:
dst = vpc->r_result[fdst->DstRegister.Index];
dst = vpc->r_result[fdst->Register.Index];
break;
case TGSI_FILE_TEMPORARY:
dst = vpc->r_temp[fdst->DstRegister.Index];
dst = vpc->r_temp[fdst->Register.Index];
break;
case TGSI_FILE_ADDRESS:
dst = vpc->r_address[fdst->DstRegister.Index];
dst = vpc->r_address[fdst->Register.Index];
break;
default:
NOUVEAU_ERR("bad dst file\n");
@ -405,8 +405,8 @@ nv40_vertprog_parse_instruction(struct nv40_vpc *vpc,
for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
const struct tgsi_full_src_register *fsrc;
fsrc = &finst->FullSrcRegisters[i];
if (fsrc->SrcRegister.File == TGSI_FILE_TEMPORARY) {
fsrc = &finst->Src[i];
if (fsrc->Register.File == TGSI_FILE_TEMPORARY) {
src[i] = tgsi_src(vpc, fsrc);
}
}
@ -414,9 +414,9 @@ nv40_vertprog_parse_instruction(struct nv40_vpc *vpc,
for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
const struct tgsi_full_src_register *fsrc;
fsrc = &finst->FullSrcRegisters[i];
fsrc = &finst->Src[i];
switch (fsrc->SrcRegister.File) {
switch (fsrc->Register.File) {
case TGSI_FILE_INPUT:
case TGSI_FILE_CONSTANT:
case TGSI_FILE_TEMPORARY:
@ -427,10 +427,10 @@ nv40_vertprog_parse_instruction(struct nv40_vpc *vpc,
break;
}
switch (fsrc->SrcRegister.File) {
switch (fsrc->Register.File) {
case TGSI_FILE_INPUT:
if (ai == -1 || ai == fsrc->SrcRegister.Index) {
ai = fsrc->SrcRegister.Index;
if (ai == -1 || ai == fsrc->Register.Index) {
ai = fsrc->Register.Index;
src[i] = tgsi_src(vpc, fsrc);
} else {
src[i] = temp(vpc);
@ -440,8 +440,8 @@ nv40_vertprog_parse_instruction(struct nv40_vpc *vpc,
break;
case TGSI_FILE_CONSTANT:
if ((ci == -1 && ii == -1) ||
ci == fsrc->SrcRegister.Index) {
ci = fsrc->SrcRegister.Index;
ci == fsrc->Register.Index) {
ci = fsrc->Register.Index;
src[i] = tgsi_src(vpc, fsrc);
} else {
src[i] = temp(vpc);
@ -451,8 +451,8 @@ nv40_vertprog_parse_instruction(struct nv40_vpc *vpc,
break;
case TGSI_FILE_IMMEDIATE:
if ((ci == -1 && ii == -1) ||
ii == fsrc->SrcRegister.Index) {
ii = fsrc->SrcRegister.Index;
ii == fsrc->Register.Index) {
ii = fsrc->Register.Index;
src[i] = tgsi_src(vpc, fsrc);
} else {
src[i] = temp(vpc);
@ -469,8 +469,8 @@ nv40_vertprog_parse_instruction(struct nv40_vpc *vpc,
}
}
dst = tgsi_dst(vpc, &finst->FullDstRegisters[0]);
mask = tgsi_mask(finst->FullDstRegisters[0].DstRegister.WriteMask);
dst = tgsi_dst(vpc, &finst->Dst[0]);
mask = tgsi_mask(finst->Dst[0].Register.WriteMask);
switch (finst->Instruction.Opcode) {
case TGSI_OPCODE_ABS:
@ -577,19 +577,19 @@ static boolean
nv40_vertprog_parse_decl_output(struct nv40_vpc *vpc,
const struct tgsi_full_declaration *fdec)
{
unsigned idx = fdec->DeclarationRange.First;
unsigned idx = fdec->Range.First;
int hw;
switch (fdec->Semantic.SemanticName) {
switch (fdec->Semantic.Name) {
case TGSI_SEMANTIC_POSITION:
hw = NV40_VP_INST_DEST_POS;
vpc->hpos_idx = idx;
break;
case TGSI_SEMANTIC_COLOR:
if (fdec->Semantic.SemanticIndex == 0) {
if (fdec->Semantic.Index == 0) {
hw = NV40_VP_INST_DEST_COL0;
} else
if (fdec->Semantic.SemanticIndex == 1) {
if (fdec->Semantic.Index == 1) {
hw = NV40_VP_INST_DEST_COL1;
} else {
NOUVEAU_ERR("bad colour semantic index\n");
@ -597,10 +597,10 @@ nv40_vertprog_parse_decl_output(struct nv40_vpc *vpc,
}
break;
case TGSI_SEMANTIC_BCOLOR:
if (fdec->Semantic.SemanticIndex == 0) {
if (fdec->Semantic.Index == 0) {
hw = NV40_VP_INST_DEST_BFC0;
} else
if (fdec->Semantic.SemanticIndex == 1) {
if (fdec->Semantic.Index == 1) {
hw = NV40_VP_INST_DEST_BFC1;
} else {
NOUVEAU_ERR("bad bcolour semantic index\n");
@ -614,8 +614,8 @@ nv40_vertprog_parse_decl_output(struct nv40_vpc *vpc,
hw = NV40_VP_INST_DEST_PSZ;
break;
case TGSI_SEMANTIC_GENERIC:
if (fdec->Semantic.SemanticIndex <= 7) {
hw = NV40_VP_INST_DEST_TC(fdec->Semantic.SemanticIndex);
if (fdec->Semantic.Index <= 7) {
hw = NV40_VP_INST_DEST_TC(fdec->Semantic.Index);
} else {
NOUVEAU_ERR("bad generic semantic index\n");
return FALSE;
@ -652,16 +652,16 @@ nv40_vertprog_prepare(struct nv40_vpc *vpc)
fdec = &p.FullToken.FullDeclaration;
switch (fdec->Declaration.File) {
case TGSI_FILE_TEMPORARY:
if (fdec->DeclarationRange.Last > high_temp) {
if (fdec->Range.Last > high_temp) {
high_temp =
fdec->DeclarationRange.Last;
fdec->Range.Last;
}
break;
#if 0 /* this would be nice.. except gallium doesn't track it */
case TGSI_FILE_ADDRESS:
if (fdec->DeclarationRange.Last > high_addr) {
if (fdec->Range.Last > high_addr) {
high_addr =
fdec->DeclarationRange.Last;
fdec->Range.Last;
}
break;
#endif
@ -681,11 +681,11 @@ nv40_vertprog_prepare(struct nv40_vpc *vpc)
const struct tgsi_full_dst_register *fdst;
finst = &p.FullToken.FullInstruction;
fdst = &finst->FullDstRegisters[0];
fdst = &finst->Dst[0];
if (fdst->DstRegister.File == TGSI_FILE_ADDRESS) {
if (fdst->DstRegister.Index > high_addr)
high_addr = fdst->DstRegister.Index;
if (fdst->Register.File == TGSI_FILE_ADDRESS) {
if (fdst->Register.Index > high_addr)
high_addr = fdst->Register.Index;
}
}

108
src/gallium/drivers/nv50/nv50_program.c
View file

@ -1541,10 +1541,10 @@ negate_supported(const struct tgsi_full_instruction *insn, int i)
for (s = 0; s < insn->Instruction.NumSrcRegs; ++s) {
if (s == i)
continue;
if ((insn->FullSrcRegisters[s].SrcRegister.Index ==
insn->FullSrcRegisters[i].SrcRegister.Index) &&
(insn->FullSrcRegisters[s].SrcRegister.File ==
insn->FullSrcRegisters[i].SrcRegister.File))
if ((insn->Src[s].Register.Index ==
insn->Src[i].Register.Index) &&
(insn->Src[s].Register.File ==
insn->Src[i].Register.File))
return FALSE;
}
@ -1555,7 +1555,7 @@ negate_supported(const struct tgsi_full_instruction *insn, int i)
static unsigned
nv50_tgsi_src_mask(const struct tgsi_full_instruction *insn, int c)
{
unsigned x, mask = insn->FullDstRegisters[0].DstRegister.WriteMask;
unsigned x, mask = insn->Dst[0].Register.WriteMask;
switch (insn->Instruction.Opcode) {
case TGSI_OPCODE_COS:
@ -1581,10 +1581,10 @@ nv50_tgsi_src_mask(const struct tgsi_full_instruction *insn, int c)
case TGSI_OPCODE_TEX:
case TGSI_OPCODE_TXP:
{
const struct tgsi_instruction_ext_texture *tex;
const struct tgsi_instruction_texture *tex;
assert(insn->Instruction.Extended);
tex = &insn->InstructionExtTexture;
assert(insn->Instruction.Texture);
tex = &insn->Texture;
mask = 0x7;
if (insn->Instruction.Opcode == TGSI_OPCODE_TXP)
@ -1618,17 +1618,17 @@ nv50_tgsi_src_mask(const struct tgsi_full_instruction *insn, int c)
static struct nv50_reg *
tgsi_dst(struct nv50_pc *pc, int c, const struct tgsi_full_dst_register *dst)
{
switch (dst->DstRegister.File) {
switch (dst->Register.File) {
case TGSI_FILE_TEMPORARY:
return &pc->temp[dst->DstRegister.Index * 4 + c];
return &pc->temp[dst->Register.Index * 4 + c];
case TGSI_FILE_OUTPUT:
return &pc->result[dst->DstRegister.Index * 4 + c];
return &pc->result[dst->Register.Index * 4 + c];
case TGSI_FILE_ADDRESS:
{
struct nv50_reg *r = pc->addr[dst->DstRegister.Index * 4 + c];
struct nv50_reg *r = pc->addr[dst->Register.Index * 4 + c];
if (!r) {
r = alloc_addr(pc, NULL);
pc->addr[dst->DstRegister.Index * 4 + c] = r;
pc->addr[dst->Register.Index * 4 + c] = r;
}
assert(r);
return r;
@ -1650,8 +1650,8 @@ tgsi_src(struct nv50_pc *pc, int chan, const struct tgsi_full_src_register *src,
struct nv50_reg *temp;
unsigned sgn, c, swz;
if (src->SrcRegister.File != TGSI_FILE_CONSTANT)
assert(!src->SrcRegister.Indirect);
if (src->Register.File != TGSI_FILE_CONSTANT)
assert(!src->Register.Indirect);
sgn = tgsi_util_get_full_src_register_sign_mode(src, chan);
@ -1661,16 +1661,16 @@ tgsi_src(struct nv50_pc *pc, int chan, const struct tgsi_full_src_register *src,
case TGSI_SWIZZLE_Y:
case TGSI_SWIZZLE_Z:
case TGSI_SWIZZLE_W:
switch (src->SrcRegister.File) {
switch (src->Register.File) {
case TGSI_FILE_INPUT:
r = &pc->attr[src->SrcRegister.Index * 4 + c];
r = &pc->attr[src->Register.Index * 4 + c];
break;
case TGSI_FILE_TEMPORARY:
r = &pc->temp[src->SrcRegister.Index * 4 + c];
r = &pc->temp[src->Register.Index * 4 + c];
break;
case TGSI_FILE_CONSTANT:
if (!src->SrcRegister.Indirect) {
r = &pc->param[src->SrcRegister.Index * 4 + c];
if (!src->Register.Indirect) {
r = &pc->param[src->Register.Index * 4 + c];
break;
}
/* Indicate indirection by setting r->acc < 0 and
@ -1678,19 +1678,19 @@ tgsi_src(struct nv50_pc *pc, int chan, const struct tgsi_full_src_register *src,
*/
r = MALLOC_STRUCT(nv50_reg);
swz = tgsi_util_get_src_register_swizzle(
&src->SrcRegisterInd, 0);
&src->Indirect, 0);
ctor_reg(r, P_CONST,
src->SrcRegisterInd.Index * 4 + swz,
src->SrcRegister.Index * 4 + c);
src->Indirect.Index * 4 + swz,
src->Register.Index * 4 + c);
r->acc = -1;
break;
case TGSI_FILE_IMMEDIATE:
r = &pc->immd[src->SrcRegister.Index * 4 + c];
r = &pc->immd[src->Register.Index * 4 + c];
break;
case TGSI_FILE_SAMPLER:
break;
case TGSI_FILE_ADDRESS:
r = pc->addr[src->SrcRegister.Index * 4 + c];
r = pc->addr[src->Register.Index * 4 + c];
assert(r);
break;
default:
@ -1856,29 +1856,29 @@ nv50_program_tx_insn(struct nv50_pc *pc,
unsigned mask, sat, unit;
int i, c;
mask = inst->FullDstRegisters[0].DstRegister.WriteMask;
mask = inst->Dst[0].Register.WriteMask;
sat = inst->Instruction.Saturate == TGSI_SAT_ZERO_ONE;
memset(src, 0, sizeof(src));
for (c = 0; c < 4; c++) {
if ((mask & (1 << c)) && !pc->r_dst[c])
dst[c] = tgsi_dst(pc, c, &inst->FullDstRegisters[0]);
dst[c] = tgsi_dst(pc, c, &inst->Dst[0]);
else
dst[c] = pc->r_dst[c];
rdst[c] = dst[c];
}
for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
const struct tgsi_full_src_register *fs = &inst->FullSrcRegisters[i];
const struct tgsi_full_src_register *fs = &inst->Src[i];
unsigned src_mask;
boolean neg_supp;
src_mask = nv50_tgsi_src_mask(inst, i);
neg_supp = negate_supported(inst, i);
if (fs->SrcRegister.File == TGSI_FILE_SAMPLER)
unit = fs->SrcRegister.Index;
if (fs->Register.File == TGSI_FILE_SAMPLER)
unit = fs->Register.Index;
for (c = 0; c < 4; c++)
if (src_mask & (1 << c))
@ -2187,11 +2187,11 @@ nv50_program_tx_insn(struct nv50_pc *pc,
break;
case TGSI_OPCODE_TEX:
emit_tex(pc, dst, mask, src[0], unit,
inst->InstructionExtTexture.Texture, FALSE);
inst->Texture.Texture, FALSE);
break;
case TGSI_OPCODE_TXP:
emit_tex(pc, dst, mask, src[0], unit,
inst->InstructionExtTexture.Texture, TRUE);
inst->Texture.Texture, TRUE);
break;
case TGSI_OPCODE_TRUNC:
for (c = 0; c < 4; c++) {
@ -2270,7 +2270,7 @@ prep_inspect_insn(struct nv50_pc *pc, const struct tgsi_full_instruction *insn)
const struct tgsi_dst_register *dst;
unsigned i, c, k, mask;
dst = &insn->FullDstRegisters[0].DstRegister;
dst = &insn->Dst[0].Register;
mask = dst->WriteMask;
if (dst->File == TGSI_FILE_TEMPORARY)
@ -2288,12 +2288,12 @@ prep_inspect_insn(struct nv50_pc *pc, const struct tgsi_full_instruction *insn)
}
for (i = 0; i < insn->Instruction.NumSrcRegs; i++) {
src = &insn->FullSrcRegisters[i];
src = &insn->Src[i];
if (src->SrcRegister.File == TGSI_FILE_TEMPORARY)
if (src->Register.File == TGSI_FILE_TEMPORARY)
reg = pc->temp;
else
if (src->SrcRegister.File == TGSI_FILE_INPUT)
if (src->Register.File == TGSI_FILE_INPUT)
reg = pc->attr;
else
continue;
@ -2305,7 +2305,7 @@ prep_inspect_insn(struct nv50_pc *pc, const struct tgsi_full_instruction *insn)
continue;
k = tgsi_util_get_full_src_register_swizzle(src, c);
reg[src->SrcRegister.Index * 4 + k].acc = pc->insn_nr;
reg[src->Register.Index * 4 + k].acc = pc->insn_nr;
}
}
}
@ -2365,13 +2365,13 @@ static struct nv50_reg *
tgsi_broadcast_dst(struct nv50_pc *pc,
const struct tgsi_full_dst_register *fd, unsigned mask)
{
if (fd->DstRegister.File == TGSI_FILE_TEMPORARY) {
int c = ffs(~mask & fd->DstRegister.WriteMask);
if (fd->Register.File == TGSI_FILE_TEMPORARY) {
int c = ffs(~mask & fd->Register.WriteMask);
if (c)
return tgsi_dst(pc, c - 1, fd);
} else {
int c = ffs(fd->DstRegister.WriteMask) - 1;
if ((1 << c) == fd->DstRegister.WriteMask)
int c = ffs(fd->Register.WriteMask) - 1;
if ((1 << c) == fd->Register.WriteMask)
return tgsi_dst(pc, c, fd);
}
@ -2385,7 +2385,7 @@ static unsigned
nv50_tgsi_scan_swizzle(const struct tgsi_full_instruction *insn,
unsigned rdep[4])
{
const struct tgsi_full_dst_register *fd = &insn->FullDstRegisters[0];
const struct tgsi_full_dst_register *fd = &insn->Dst[0];
const struct tgsi_full_src_register *fs;
unsigned i, deqs = 0;
@ -2396,9 +2396,9 @@ nv50_tgsi_scan_swizzle(const struct tgsi_full_instruction *insn,
unsigned chn, mask = nv50_tgsi_src_mask(insn, i);
boolean neg_supp = negate_supported(insn, i);
fs = &insn->FullSrcRegisters[i];
if (fs->SrcRegister.File != fd->DstRegister.File ||
fs->SrcRegister.Index != fd->DstRegister.Index)
fs = &insn->Src[i];
if (fs->Register.File != fd->Register.File ||
fs->Register.Index != fd->Register.Index)
continue;
for (chn = 0; chn < 4; ++chn) {
@ -2409,7 +2409,7 @@ nv50_tgsi_scan_swizzle(const struct tgsi_full_instruction *insn,
c = tgsi_util_get_full_src_register_swizzle(fs, chn);
s = tgsi_util_get_full_src_register_sign_mode(fs, chn);
if (!(fd->DstRegister.WriteMask & (1 << c)))
if (!(fd->Register.WriteMask & (1 << c)))
continue;
/* no danger if src is copied to TEMP first */
@ -2433,7 +2433,7 @@ nv50_tgsi_insn(struct nv50_pc *pc, const union tgsi_full_token *tok)
const struct tgsi_full_dst_register *fd;
unsigned i, deqs, rdep[4], m[4];
fd = &tok->FullInstruction.FullDstRegisters[0];
fd = &tok->FullInstruction.Dst[0];
deqs = nv50_tgsi_scan_swizzle(&insn, rdep);
if (is_scalar_op(insn.Instruction.Opcode)) {
@ -2452,10 +2452,10 @@ nv50_tgsi_insn(struct nv50_pc *pc, const union tgsi_full_token *tok)
for (i = 0; i < 4; ++i) {
assert(pc->r_dst[m[i]] == NULL);
insn.FullDstRegisters[0].DstRegister.WriteMask =
fd->DstRegister.WriteMask & (1 << m[i]);
insn.Dst[0].Register.WriteMask =
fd->Register.WriteMask & (1 << m[i]);
if (!insn.FullDstRegisters[0].DstRegister.WriteMask)
if (!insn.Dst[0].Register.WriteMask)
continue;
if (deqs & (1 << i))
@ -2553,8 +2553,8 @@ nv50_program_tx_prep(struct nv50_pc *pc)
unsigned si, last, first, mode;
d = &tp.FullToken.FullDeclaration;
first = d->DeclarationRange.First;
last = d->DeclarationRange.Last;
first = d->Range.First;
last = d->Range.Last;
switch (d->Declaration.File) {
case TGSI_FILE_TEMPORARY:
@ -2564,8 +2564,8 @@ nv50_program_tx_prep(struct nv50_pc *pc)
p->type == PIPE_SHADER_FRAGMENT)
break;
si = d->Semantic.SemanticIndex;
switch (d->Semantic.SemanticName) {
si = d->Semantic.Index;
switch (d->Semantic.Name) {
case TGSI_SEMANTIC_BCOLOR:
p->cfg.two_side[si].hw = first;
if (p->cfg.io_nr > first)

31
src/gallium/drivers/r300/r300_tgsi_to_rc.c
View file

@ -190,10 +190,10 @@ static void transform_dstreg(
struct rc_dst_register * dst,
struct tgsi_full_dst_register * src)
{
dst->File = translate_register_file(src->DstRegister.File);
dst->Index = translate_register_index(ttr, src->DstRegister.File, src->DstRegister.Index);
dst->WriteMask = src->DstRegister.WriteMask;
dst->RelAddr = src->DstRegister.Indirect;
dst->File = translate_register_file(src->Register.File);
dst->Index = translate_register_index(ttr, src->Register.File, src->Register.Index);
dst->WriteMask = src->Register.WriteMask;
dst->RelAddr = src->Register.Indirect;
}
static void transform_srcreg(
@ -201,18 +201,18 @@ static void transform_srcreg(
struct rc_src_register * dst,
struct tgsi_full_src_register * src)
{
dst->File = translate_register_file(src->SrcRegister.File);
dst->Index = translate_register_index(ttr, src->SrcRegister.File, src->SrcRegister.Index);
dst->RelAddr = src->SrcRegister.Indirect;
dst->File = translate_register_file(src->Register.File);
dst->Index = translate_register_index(ttr, src->Register.File, src->Register.Index);
dst->RelAddr = src->Register.Indirect;
dst->Swizzle = tgsi_util_get_full_src_register_swizzle(src, 0);
dst->Swizzle |= tgsi_util_get_full_src_register_swizzle(src, 1) << 3;
dst->Swizzle |= tgsi_util_get_full_src_register_swizzle(src, 2) << 6;
dst->Swizzle |= tgsi_util_get_full_src_register_swizzle(src, 3) << 9;
dst->Abs = src->SrcRegisterExtMod.Absolute;
dst->Negate = src->SrcRegister.Negate ? RC_MASK_XYZW : 0;
dst->Abs = src->Register.Absolute;
dst->Negate = src->Register.Negate ? RC_MASK_XYZW : 0;
}
static void transform_texture(struct rc_instruction * dst, struct tgsi_instruction_ext_texture src)
static void transform_texture(struct rc_instruction * dst, struct tgsi_instruction_texture src)
{
switch(src.Texture) {
case TGSI_TEXTURE_1D:
@ -258,17 +258,18 @@ static void transform_instruction(struct tgsi_to_rc * ttr, struct tgsi_full_inst
dst->U.I.SaturateMode = translate_saturate(src->Instruction.Saturate);
if (src->Instruction.NumDstRegs)
transform_dstreg(ttr, &dst->U.I.DstReg, &src->FullDstRegisters[0]);
transform_dstreg(ttr, &dst->U.I.DstReg, &src->Dst[0]);
for(i = 0; i < src->Instruction.NumSrcRegs; ++i) {
if (src->FullSrcRegisters[i].SrcRegister.File == TGSI_FILE_SAMPLER)
dst->U.I.TexSrcUnit = src->FullSrcRegisters[i].SrcRegister.Index;
if (src->Src[i].Register.File == TGSI_FILE_SAMPLER)
dst->U.I.TexSrcUnit = src->Src[i].Register.Index;
else
transform_srcreg(ttr, &dst->U.I.SrcReg[i], &src->FullSrcRegisters[i]);
transform_srcreg(ttr, &dst->U.I.SrcReg[i], &src->Src[i]);
}
/* Texturing. */
transform_texture(dst, src->InstructionExtTexture);
if (src->Instruction.Texture)
transform_texture(dst, src->Texture);
}
static void handle_immediate(struct tgsi_to_rc * ttr, struct tgsi_full_immediate * imm)

2
src/gallium/drivers/svga/svga_pipe_vs.c
View file

@ -48,7 +48,7 @@ static const struct tgsi_token *substitute_vs(
static struct tgsi_token tokens[300];
const char *text =
"VERT1.1\n"
"VERT\n"
"DCL IN[0]\n"
"DCL IN[1]\n"
"DCL IN[2]\n"

38
src/gallium/drivers/svga/svga_tgsi_decl_sm20.c
View file

@ -46,7 +46,7 @@ static boolean ps20_input( struct svga_shader_emitter *emit,
dcl.values[0] = 0;
dcl.values[1] = 0;
switch (semantic.SemanticName) {
switch (semantic.Name) {
case TGSI_SEMANTIC_POSITION:
/* Special case:
*/
@ -55,15 +55,15 @@ static boolean ps20_input( struct svga_shader_emitter *emit,
break;
case TGSI_SEMANTIC_COLOR:
reg = src_register( SVGA3DREG_INPUT,
semantic.SemanticIndex );
semantic.Index );
break;
case TGSI_SEMANTIC_FOG:
assert(semantic.SemanticIndex == 0);
assert(semantic.Index == 0);
reg = src_register( SVGA3DREG_TEXTURE, 0 );
break;
case TGSI_SEMANTIC_GENERIC:
reg = src_register( SVGA3DREG_TEXTURE,
semantic.SemanticIndex + 1 );
semantic.Index + 1 );
break;
default:
assert(0);
@ -90,16 +90,16 @@ static boolean ps20_output( struct svga_shader_emitter *emit,
{
SVGA3dShaderDestToken reg;
switch (semantic.SemanticName) {
switch (semantic.Name) {
case TGSI_SEMANTIC_COLOR:
if (semantic.SemanticIndex < PIPE_MAX_COLOR_BUFS) {
unsigned cbuf = semantic.SemanticIndex;
if (semantic.Index < PIPE_MAX_COLOR_BUFS) {
unsigned cbuf = semantic.Index;
emit->output_map[idx] = dst_register( SVGA3DREG_TEMP,
emit->nr_hw_temp++ );
emit->temp_col[cbuf] = emit->output_map[idx];
emit->true_col[cbuf] = dst_register( SVGA3DREG_COLOROUT,
semantic.SemanticIndex );
semantic.Index );
}
else {
assert(0);
@ -111,7 +111,7 @@ static boolean ps20_output( struct svga_shader_emitter *emit,
emit->nr_hw_temp++ );
emit->temp_pos = emit->output_map[idx];
emit->true_pos = dst_register( SVGA3DREG_DEPTHOUT,
semantic.SemanticIndex );
semantic.Index );
break;
default:
assert(0);
@ -169,9 +169,9 @@ static boolean vs20_output( struct svga_shader_emitter *emit,
/* Just build the register map table:
*/
switch (semantic.SemanticName) {
switch (semantic.Name) {
case TGSI_SEMANTIC_POSITION:
assert(semantic.SemanticIndex == 0);
assert(semantic.Index == 0);
emit->output_map[idx] = dst_register( SVGA3DREG_TEMP,
emit->nr_hw_temp++ );
emit->temp_pos = emit->output_map[idx];
@ -179,7 +179,7 @@ static boolean vs20_output( struct svga_shader_emitter *emit,
SVGA3DRASTOUT_POSITION);
break;
case TGSI_SEMANTIC_PSIZE:
assert(semantic.SemanticIndex == 0);
assert(semantic.Index == 0);
emit->output_map[idx] = dst_register( SVGA3DREG_TEMP,
emit->nr_hw_temp++ );
emit->temp_psiz = emit->output_map[idx];
@ -187,17 +187,17 @@ static boolean vs20_output( struct svga_shader_emitter *emit,
SVGA3DRASTOUT_PSIZE );
break;
case TGSI_SEMANTIC_FOG:
assert(semantic.SemanticIndex == 0);
assert(semantic.Index == 0);
emit->output_map[idx] = dst_register( SVGA3DREG_TEXCRDOUT, 0 );
break;
case TGSI_SEMANTIC_COLOR:
/* oD0 */
emit->output_map[idx] = dst_register( SVGA3DREG_ATTROUT,
semantic.SemanticIndex );
semantic.Index );
break;
case TGSI_SEMANTIC_GENERIC:
emit->output_map[idx] = dst_register( SVGA3DREG_TEXCRDOUT,
semantic.SemanticIndex + 1 );
semantic.Index + 1 );
break;
default:
assert(0);
@ -230,15 +230,15 @@ static boolean ps20_sampler( struct svga_shader_emitter *emit,
boolean svga_translate_decl_sm20( struct svga_shader_emitter *emit,
const struct tgsi_full_declaration *decl )
{
unsigned first = decl->DeclarationRange.First;
unsigned last = decl->DeclarationRange.Last;
unsigned first = decl->Range.First;
unsigned last = decl->Range.Last;
unsigned semantic = 0;
unsigned semantic_idx = 0;
unsigned idx;
if (decl->Declaration.Semantic) {
semantic = decl->Semantic.SemanticName;
semantic_idx = decl->Semantic.SemanticIndex;
semantic = decl->Semantic.Name;
semantic_idx = decl->Semantic.Index;
}
for( idx = first; idx <= last; idx++ ) {

42
src/gallium/drivers/svga/svga_tgsi_decl_sm30.c
View file

@ -35,35 +35,35 @@ static boolean translate_vs_ps_semantic( struct tgsi_declaration_semantic semant
unsigned *usage,
unsigned *idx )
{
switch (semantic.SemanticName) {
switch (semantic.Name) {
case TGSI_SEMANTIC_POSITION:
*idx = semantic.SemanticIndex;
*idx = semantic.Index;
*usage = SVGA3D_DECLUSAGE_POSITION;
break;
case TGSI_SEMANTIC_COLOR:
*idx = semantic.SemanticIndex;
*idx = semantic.Index;
*usage = SVGA3D_DECLUSAGE_COLOR;
break;
case TGSI_SEMANTIC_BCOLOR:
*idx = semantic.SemanticIndex + 2; /* sharing with COLOR */
*idx = semantic.Index + 2; /* sharing with COLOR */
*usage = SVGA3D_DECLUSAGE_COLOR;
break;
case TGSI_SEMANTIC_FOG:
*idx = 0;
assert(semantic.SemanticIndex == 0);
assert(semantic.Index == 0);
*usage = SVGA3D_DECLUSAGE_TEXCOORD;
break;
case TGSI_SEMANTIC_PSIZE:
*idx = semantic.SemanticIndex;
*idx = semantic.Index;
*usage = SVGA3D_DECLUSAGE_PSIZE;
break;
case TGSI_SEMANTIC_GENERIC:
*idx = semantic.SemanticIndex + 1; /* texcoord[0] is reserved for fog */
*idx = semantic.Index + 1; /* texcoord[0] is reserved for fog */
*usage = SVGA3D_DECLUSAGE_TEXCOORD;
break;
case TGSI_SEMANTIC_NORMAL:
*idx = semantic.SemanticIndex;
*idx = semantic.Index;
*usage = SVGA3D_DECLUSAGE_NORMAL;
break;
default:
@ -120,7 +120,7 @@ static boolean ps30_input( struct svga_shader_emitter *emit,
unsigned usage, index;
SVGA3dShaderDestToken reg;
if (semantic.SemanticName == TGSI_SEMANTIC_POSITION) {
if (semantic.Name == TGSI_SEMANTIC_POSITION) {
emit->input_map[idx] = src_register( SVGA3DREG_MISCTYPE,
SVGA3DMISCREG_POSITION );
@ -135,7 +135,7 @@ static boolean ps30_input( struct svga_shader_emitter *emit,
return emit_decl( emit, reg, 0, 0 );
}
else if (emit->key.fkey.light_twoside &&
(semantic.SemanticName == TGSI_SEMANTIC_COLOR)) {
(semantic.Name == TGSI_SEMANTIC_COLOR)) {
if (!translate_vs_ps_semantic( semantic, &usage, &index ))
return FALSE;
@ -150,7 +150,7 @@ static boolean ps30_input( struct svga_shader_emitter *emit,
if (!emit_decl( emit, reg, usage, index ))
return FALSE;
semantic.SemanticName = TGSI_SEMANTIC_BCOLOR;
semantic.Name = TGSI_SEMANTIC_BCOLOR;
if (!translate_vs_ps_semantic( semantic, &usage, &index ))
return FALSE;
@ -164,7 +164,7 @@ static boolean ps30_input( struct svga_shader_emitter *emit,
return TRUE;
}
else if (semantic.SemanticName == TGSI_SEMANTIC_FACE) {
else if (semantic.Name == TGSI_SEMANTIC_FACE) {
if (!emit_vface_decl( emit ))
return FALSE;
emit->emit_frontface = TRUE;
@ -193,17 +193,17 @@ static boolean ps30_output( struct svga_shader_emitter *emit,
{
SVGA3dShaderDestToken reg;
switch (semantic.SemanticName) {
switch (semantic.Name) {
case TGSI_SEMANTIC_COLOR:
emit->output_map[idx] = dst_register( SVGA3DREG_COLOROUT,
semantic.SemanticIndex );
semantic.Index );
break;
case TGSI_SEMANTIC_POSITION:
emit->output_map[idx] = dst_register( SVGA3DREG_TEMP,
emit->nr_hw_temp++ );
emit->temp_pos = emit->output_map[idx];
emit->true_pos = dst_register( SVGA3DREG_DEPTHOUT,
semantic.SemanticIndex );
semantic.Index );
break;
default:
assert(0);
@ -283,14 +283,14 @@ static boolean vs30_output( struct svga_shader_emitter *emit,
dcl.index = index;
dcl.values[0] |= 1<<31;
if (semantic.SemanticName == TGSI_SEMANTIC_POSITION) {
if (semantic.Name == TGSI_SEMANTIC_POSITION) {
assert(idx == 0);
emit->output_map[idx] = dst_register( SVGA3DREG_TEMP,
emit->nr_hw_temp++ );
emit->temp_pos = emit->output_map[idx];
emit->true_pos = dcl.dst;
}
else if (semantic.SemanticName == TGSI_SEMANTIC_PSIZE) {
else if (semantic.Name == TGSI_SEMANTIC_PSIZE) {
emit->output_map[idx] = dst_register( SVGA3DREG_TEMP,
emit->nr_hw_temp++ );
emit->temp_psiz = emit->output_map[idx];
@ -335,15 +335,15 @@ static boolean ps30_sampler( struct svga_shader_emitter *emit,
boolean svga_translate_decl_sm30( struct svga_shader_emitter *emit,
const struct tgsi_full_declaration *decl )
{
unsigned first = decl->DeclarationRange.First;
unsigned last = decl->DeclarationRange.Last;
unsigned first = decl->Range.First;
unsigned last = decl->Range.Last;
unsigned semantic = 0;
unsigned semantic_idx = 0;
unsigned idx;
if (decl->Declaration.Semantic) {
semantic = decl->Semantic.SemanticName;
semantic_idx = decl->Semantic.SemanticIndex;
semantic = decl->Semantic.Name;
semantic_idx = decl->Semantic.Index;
}
for( idx = first; idx <= last; idx++ ) {

176
src/gallium/drivers/svga/svga_tgsi_insn.c
View file

@ -96,24 +96,24 @@ translate_dst_register( struct svga_shader_emitter *emit,
const struct tgsi_full_instruction *insn,
unsigned idx )
{
const struct tgsi_full_dst_register *reg = &insn->FullDstRegisters[idx];
const struct tgsi_full_dst_register *reg = &insn->Dst[idx];
SVGA3dShaderDestToken dest;
switch (reg->DstRegister.File) {
switch (reg->Register.File) {
case TGSI_FILE_OUTPUT:
/* Output registers encode semantic information in their name.
* Need to lookup a table built at decl time:
*/
dest = emit->output_map[reg->DstRegister.Index];
dest = emit->output_map[reg->Register.Index];
break;
default:
dest = dst_register( translate_file( reg->DstRegister.File ),
reg->DstRegister.Index );
dest = dst_register( translate_file( reg->Register.File ),
reg->Register.Index );
break;
}
dest.mask = reg->DstRegister.WriteMask;
dest.mask = reg->Register.WriteMask;
if (insn->Instruction.Saturate)
dest.dstMod = SVGA3DDSTMOD_SATURATE;
@ -176,33 +176,33 @@ translate_src_register( const struct svga_shader_emitter *emit,
{
struct src_register src;
switch (reg->SrcRegister.File) {
switch (reg->Register.File) {
case TGSI_FILE_INPUT:
/* Input registers are referred to by their semantic name rather
* than by index. Use the mapping build up from the decls:
*/
src = emit->input_map[reg->SrcRegister.Index];
src = emit->input_map[reg->Register.Index];
break;
case TGSI_FILE_IMMEDIATE:
/* Immediates are appended after TGSI constants in the D3D
* constant buffer.
*/
src = src_register( translate_file( reg->SrcRegister.File ),
reg->SrcRegister.Index +
src = src_register( translate_file( reg->Register.File ),
reg->Register.Index +
emit->imm_start );
break;
default:
src = src_register( translate_file( reg->SrcRegister.File ),
reg->SrcRegister.Index );
src = src_register( translate_file( reg->Register.File ),
reg->Register.Index );
break;
}
/* Indirect addressing (for coninstant buffer lookups only)
*/
if (reg->SrcRegister.Indirect)
if (reg->Register.Indirect)
{
/* we shift the offset towards the minimum */
if (svga_arl_needs_adjustment( emit )) {
@ -213,28 +213,28 @@ translate_src_register( const struct svga_shader_emitter *emit,
/* Not really sure what should go in the second token:
*/
src.indirect = src_token( SVGA3DREG_ADDR,
reg->SrcRegisterInd.Index );
reg->Indirect.Index );
src.indirect.swizzle = SWIZZLE_XXXX;
}
src = swizzle( src,
reg->SrcRegister.SwizzleX,
reg->SrcRegister.SwizzleY,
reg->SrcRegister.SwizzleZ,
reg->SrcRegister.SwizzleW );
reg->Register.SwizzleX,
reg->Register.SwizzleY,
reg->Register.SwizzleZ,
reg->Register.SwizzleW );
/* src.mod isn't a bitfield, unfortunately:
* See tgsi_util_get_full_src_register_sign_mode for implementation details.
*/
if (reg->SrcRegisterExtMod.Absolute) {
if (reg->SrcRegisterExtMod.Negate)
if (reg->Register.Absolute) {
if (reg->Register.Negate)
src.base.srcMod = SVGA3DSRCMOD_ABSNEG;
else
src.base.srcMod = SVGA3DSRCMOD_ABS;
}
else {
if (reg->SrcRegister.Negate != reg->SrcRegisterExtMod.Negate)
if (reg->Register.Negate)
src.base.srcMod = SVGA3DSRCMOD_NEG;
else
src.base.srcMod = SVGA3DSRCMOD_NONE;
@ -629,7 +629,7 @@ static boolean emit_fake_arl(struct svga_shader_emitter *emit,
const struct tgsi_full_instruction *insn)
{
const struct src_register src0 = translate_src_register(
emit, &insn->FullSrcRegisters[0] );
emit, &insn->Src[0] );
struct src_register src1 = get_fake_arl_const( emit );
SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
SVGA3dShaderDestToken tmp = get_temp( emit );
@ -653,7 +653,7 @@ static boolean emit_if(struct svga_shader_emitter *emit,
const struct tgsi_full_instruction *insn)
{
const struct src_register src = translate_src_register(
emit, &insn->FullSrcRegisters[0] );
emit, &insn->Src[0] );
struct src_register zero = get_zero_immediate( emit );
SVGA3dShaderInstToken if_token = inst_token( SVGA3DOP_IFC );
@ -690,7 +690,7 @@ static boolean emit_floor(struct svga_shader_emitter *emit,
{
SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
const struct src_register src0 = translate_src_register(
emit, &insn->FullSrcRegisters[0] );
emit, &insn->Src[0] );
SVGA3dShaderDestToken temp = get_temp( emit );
/* FRC TMP, SRC */
@ -716,11 +716,11 @@ static boolean emit_cmp(struct svga_shader_emitter *emit,
{
SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
const struct src_register src0 = translate_src_register(
emit, &insn->FullSrcRegisters[0] );
emit, &insn->Src[0] );
const struct src_register src1 = translate_src_register(
emit, &insn->FullSrcRegisters[1] );
emit, &insn->Src[1] );
const struct src_register src2 = translate_src_register(
emit, &insn->FullSrcRegisters[2] );
emit, &insn->Src[2] );
/* CMP DST, SRC0, SRC2, SRC1 */
return submit_op3( emit, inst_token( SVGA3DOP_CMP ), dst, src0, src2, src1);
@ -740,9 +740,9 @@ static boolean emit_div(struct svga_shader_emitter *emit,
{
SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
const struct src_register src0 = translate_src_register(
emit, &insn->FullSrcRegisters[0] );
emit, &insn->Src[0] );
const struct src_register src1 = translate_src_register(
emit, &insn->FullSrcRegisters[1] );
emit, &insn->Src[1] );
SVGA3dShaderDestToken temp = get_temp( emit );
int i;
@ -782,9 +782,9 @@ static boolean emit_dp2(struct svga_shader_emitter *emit,
{
SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
const struct src_register src0 = translate_src_register(
emit, &insn->FullSrcRegisters[0] );
emit, &insn->Src[0] );
const struct src_register src1 = translate_src_register(
emit, &insn->FullSrcRegisters[1] );
emit, &insn->Src[1] );
SVGA3dShaderDestToken temp = get_temp( emit );
struct src_register temp_src0, temp_src1;
@ -815,9 +815,9 @@ static boolean emit_dph(struct svga_shader_emitter *emit,
{
SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
const struct src_register src0 = translate_src_register(
emit, &insn->FullSrcRegisters[0] );
emit, &insn->Src[0] );
struct src_register src1 = translate_src_register(
emit, &insn->FullSrcRegisters[1] );
emit, &insn->Src[1] );
SVGA3dShaderDestToken temp = get_temp( emit );
/* DP3 TMP, SRC1, SRC2 */
@ -846,7 +846,7 @@ static boolean emit_nrm(struct svga_shader_emitter *emit,
{
SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
const struct src_register src0 = translate_src_register(
emit, &insn->FullSrcRegisters[0] );
emit, &insn->Src[0] );
SVGA3dShaderDestToken temp = get_temp( emit );
/* DP3 TMP, SRC, SRC */
@ -889,7 +889,7 @@ static boolean emit_sincos(struct svga_shader_emitter *emit,
{
SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
struct src_register src0 = translate_src_register(
emit, &insn->FullSrcRegisters[0] );
emit, &insn->Src[0] );
SVGA3dShaderDestToken temp = get_temp( emit );
/* SCS TMP SRC */
@ -912,7 +912,7 @@ static boolean emit_sin(struct svga_shader_emitter *emit,
{
SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
struct src_register src0 = translate_src_register(
emit, &insn->FullSrcRegisters[0] );
emit, &insn->Src[0] );
SVGA3dShaderDestToken temp = get_temp( emit );
/* SCS TMP SRC */
@ -937,7 +937,7 @@ static boolean emit_cos(struct svga_shader_emitter *emit,
{
SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
struct src_register src0 = translate_src_register(
emit, &insn->FullSrcRegisters[0] );
emit, &insn->Src[0] );
SVGA3dShaderDestToken temp = get_temp( emit );
/* SCS TMP SRC */
@ -962,9 +962,9 @@ static boolean emit_sub(struct svga_shader_emitter *emit,
{
SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
struct src_register src0 = translate_src_register(
emit, &insn->FullSrcRegisters[0] );
emit, &insn->Src[0] );
struct src_register src1 = translate_src_register(
emit, &insn->FullSrcRegisters[1] );
emit, &insn->Src[1] );
src1 = negate(src1);
@ -980,19 +980,19 @@ static boolean emit_kil(struct svga_shader_emitter *emit,
const struct tgsi_full_instruction *insn )
{
SVGA3dShaderInstToken inst;
const struct tgsi_full_src_register *reg = &insn->FullSrcRegisters[0];
const struct tgsi_full_src_register *reg = &insn->Src[0];
struct src_register src0;
inst = inst_token( SVGA3DOP_TEXKILL );
src0 = translate_src_register( emit, reg );
if (reg->SrcRegisterExtMod.Absolute ||
reg->SrcRegister.Negate != reg->SrcRegisterExtMod.Negate ||
reg->SrcRegister.Indirect ||
reg->SrcRegister.SwizzleX != 0 ||
reg->SrcRegister.SwizzleY != 1 ||
reg->SrcRegister.SwizzleZ != 2 ||
reg->SrcRegister.File != TGSI_FILE_TEMPORARY)
if (reg->Register.Absolute ||
reg->Register.Negate ||
reg->Register.Indirect ||
reg->Register.SwizzleX != 0 ||
reg->Register.SwizzleY != 1 ||
reg->Register.SwizzleZ != 2 ||
reg->Register.File != TGSI_FILE_TEMPORARY)
{
SVGA3dShaderDestToken temp = get_temp( emit );
@ -1154,9 +1154,9 @@ static boolean emit_select_op(struct svga_shader_emitter *emit,
{
SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
struct src_register src0 = translate_src_register(
emit, &insn->FullSrcRegisters[0] );
emit, &insn->Src[0] );
struct src_register src1 = translate_src_register(
emit, &insn->FullSrcRegisters[1] );
emit, &insn->Src[1] );
return emit_select( emit, compare, dst, src0, src1 );
}
@ -1189,8 +1189,8 @@ static boolean emit_tex2(struct svga_shader_emitter *emit,
return FALSE;
}
src0 = translate_src_register( emit, &insn->FullSrcRegisters[0] );
src1 = translate_src_register( emit, &insn->FullSrcRegisters[1] );
src0 = translate_src_register( emit, &insn->Src[0] );
src1 = translate_src_register( emit, &insn->Src[1] );
if (emit->key.fkey.tex[src1.base.num].unnormalized) {
struct src_register wh = get_tex_dimensions( emit, src1.base.num );
@ -1231,9 +1231,9 @@ static boolean emit_tex3(struct svga_shader_emitter *emit,
break;
}
src0 = translate_src_register( emit, &insn->FullSrcRegisters[0] );
src1 = translate_src_register( emit, &insn->FullSrcRegisters[1] );
src2 = translate_src_register( emit, &insn->FullSrcRegisters[2] );
src0 = translate_src_register( emit, &insn->Src[0] );
src1 = translate_src_register( emit, &insn->Src[1] );
src2 = translate_src_register( emit, &insn->Src[2] );
return submit_op3( emit, inst, dst, src0, src1, src2 );
}
@ -1245,9 +1245,9 @@ static boolean emit_tex(struct svga_shader_emitter *emit,
SVGA3dShaderDestToken dst =
translate_dst_register( emit, insn, 0 );
struct src_register src0 =
translate_src_register( emit, &insn->FullSrcRegisters[0] );
translate_src_register( emit, &insn->Src[0] );
struct src_register src1 =
translate_src_register( emit, &insn->FullSrcRegisters[1] );
translate_src_register( emit, &insn->Src[1] );
SVGA3dShaderDestToken tex_result;
@ -1359,7 +1359,7 @@ static boolean emit_scalar_op1( struct svga_shader_emitter *emit,
inst = inst_token( opcode );
dst = translate_dst_register( emit, insn, 0 );
src = translate_src_register( emit, &insn->FullSrcRegisters[0] );
src = translate_src_register( emit, &insn->Src[0] );
src = scalar( src, TGSI_SWIZZLE_X );
return submit_op1( emit, inst, dst, src );
@ -1370,7 +1370,7 @@ static boolean emit_simple_instruction(struct svga_shader_emitter *emit,
unsigned opcode,
const struct tgsi_full_instruction *insn )
{
const struct tgsi_full_src_register *src = insn->FullSrcRegisters;
const struct tgsi_full_src_register *src = insn->Src;
SVGA3dShaderInstToken inst;
SVGA3dShaderDestToken dst;
@ -1428,13 +1428,13 @@ static boolean emit_pow(struct svga_shader_emitter *emit,
{
SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
struct src_register src0 = translate_src_register(
emit, &insn->FullSrcRegisters[0] );
emit, &insn->Src[0] );
struct src_register src1 = translate_src_register(
emit, &insn->FullSrcRegisters[1] );
emit, &insn->Src[1] );
boolean need_tmp = FALSE;
/* POW can only output to a temporary */
if (insn->FullDstRegisters[0].DstRegister.File != TGSI_FILE_TEMPORARY)
if (insn->Dst[0].Register.File != TGSI_FILE_TEMPORARY)
need_tmp = TRUE;
/* POW src1 must not be the same register as dst */
@ -1463,9 +1463,9 @@ static boolean emit_xpd(struct svga_shader_emitter *emit,
{
SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
const struct src_register src0 = translate_src_register(
emit, &insn->FullSrcRegisters[0] );
emit, &insn->Src[0] );
const struct src_register src1 = translate_src_register(
emit, &insn->FullSrcRegisters[1] );
emit, &insn->Src[1] );
boolean need_dst_tmp = FALSE;
/* XPD can only output to a temporary */
@ -1517,11 +1517,11 @@ static boolean emit_lrp(struct svga_shader_emitter *emit,
SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
SVGA3dShaderDestToken tmp;
const struct src_register src0 = translate_src_register(
emit, &insn->FullSrcRegisters[0] );
emit, &insn->Src[0] );
const struct src_register src1 = translate_src_register(
emit, &insn->FullSrcRegisters[1] );
emit, &insn->Src[1] );
const struct src_register src2 = translate_src_register(
emit, &insn->FullSrcRegisters[2] );
emit, &insn->Src[2] );
boolean need_dst_tmp = FALSE;
/* The dst reg must not be the same as src0 or src2 */
@ -1568,9 +1568,9 @@ static boolean emit_dst_insn(struct svga_shader_emitter *emit,
SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
SVGA3dShaderDestToken tmp;
const struct src_register src0 = translate_src_register(
emit, &insn->FullSrcRegisters[0] );
emit, &insn->Src[0] );
const struct src_register src1 = translate_src_register(
emit, &insn->FullSrcRegisters[1] );
emit, &insn->Src[1] );
struct src_register zero = get_zero_immediate( emit );
boolean need_tmp = FALSE;
@ -1633,7 +1633,7 @@ static boolean emit_exp(struct svga_shader_emitter *emit,
{
SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
struct src_register src0 =
translate_src_register( emit, &insn->FullSrcRegisters[0] );
translate_src_register( emit, &insn->Src[0] );
struct src_register zero = get_zero_immediate( emit );
SVGA3dShaderDestToken fraction;
@ -1723,7 +1723,7 @@ static boolean emit_lit(struct svga_shader_emitter *emit,
SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
SVGA3dShaderDestToken tmp = get_temp( emit );
const struct src_register src0 = translate_src_register(
emit, &insn->FullSrcRegisters[0] );
emit, &insn->Src[0] );
struct src_register zero = get_zero_immediate( emit );
/* tmp = pow(src.y, src.w)
@ -1806,7 +1806,7 @@ static boolean emit_ex2( struct svga_shader_emitter *emit,
inst = inst_token( SVGA3DOP_EXP );
dst = translate_dst_register( emit, insn, 0 );
src0 = translate_src_register( emit, &insn->FullSrcRegisters[0] );
src0 = translate_src_register( emit, &insn->Src[0] );
src0 = scalar( src0, TGSI_SWIZZLE_X );
if (dst.mask != TGSI_WRITEMASK_XYZW) {
@ -1829,7 +1829,7 @@ static boolean emit_log(struct svga_shader_emitter *emit,
{
SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
struct src_register src0 =
translate_src_register( emit, &insn->FullSrcRegisters[0] );
translate_src_register( emit, &insn->Src[0] );
struct src_register zero = get_zero_immediate( emit );
SVGA3dShaderDestToken abs_tmp;
struct src_register abs_src0;
@ -1953,7 +1953,7 @@ static boolean emit_bgnsub( struct svga_shader_emitter *emit,
static boolean emit_call( struct svga_shader_emitter *emit,
const struct tgsi_full_instruction *insn )
{
unsigned position = insn->InstructionExtLabel.Label;
unsigned position = insn->Label.Label;
unsigned i;
for (i = 0; i < emit->nr_labels; i++) {
@ -2543,27 +2543,27 @@ pre_parse_instruction( struct svga_shader_emitter *emit,
const struct tgsi_full_instruction *insn,
int current_arl)
{
if (insn->FullSrcRegisters[0].SrcRegister.Indirect &&
insn->FullSrcRegisters[0].SrcRegisterInd.File == TGSI_FILE_ADDRESS) {
const struct tgsi_full_src_register *reg = &insn->FullSrcRegisters[0];
if (reg->SrcRegister.Index < 0) {
pre_parse_add_indirect(emit, reg->SrcRegister.Index, current_arl);
if (insn->Src[0].Register.Indirect &&
insn->Src[0].Indirect.File == TGSI_FILE_ADDRESS) {
const struct tgsi_full_src_register *reg = &insn->Src[0];
if (reg->Register.Index < 0) {
pre_parse_add_indirect(emit, reg->Register.Index, current_arl);
}
}
if (insn->FullSrcRegisters[1].SrcRegister.Indirect &&
insn->FullSrcRegisters[1].SrcRegisterInd.File == TGSI_FILE_ADDRESS) {
const struct tgsi_full_src_register *reg = &insn->FullSrcRegisters[1];
if (reg->SrcRegister.Index < 0) {
pre_parse_add_indirect(emit, reg->SrcRegister.Index, current_arl);
if (insn->Src[1].Register.Indirect &&
insn->Src[1].Indirect.File == TGSI_FILE_ADDRESS) {
const struct tgsi_full_src_register *reg = &insn->Src[1];
if (reg->Register.Index < 0) {
pre_parse_add_indirect(emit, reg->Register.Index, current_arl);
}
}
if (insn->FullSrcRegisters[2].SrcRegister.Indirect &&
insn->FullSrcRegisters[2].SrcRegisterInd.File == TGSI_FILE_ADDRESS) {
const struct tgsi_full_src_register *reg = &insn->FullSrcRegisters[2];
if (reg->SrcRegister.Index < 0) {
pre_parse_add_indirect(emit, reg->SrcRegister.Index, current_arl);
if (insn->Src[2].Register.Indirect &&
insn->Src[2].Indirect.File == TGSI_FILE_ADDRESS) {
const struct tgsi_full_src_register *reg = &insn->Src[2];
if (reg->Register.Index < 0) {
pre_parse_add_indirect(emit, reg->Register.Index, current_arl);
}
}

168
src/gallium/include/pipe/p_shader_tokens.h
View file

@ -35,12 +35,6 @@ extern "C" {
#include "p_compiler.h"
struct tgsi_version
{
unsigned MajorVersion : 8;
unsigned MinorVersion : 8;
unsigned Padding : 16;
};
struct tgsi_header
{
@ -66,8 +60,7 @@ struct tgsi_token
{
unsigned Type : 4; /**< TGSI_TOKEN_TYPE_x */
unsigned NrTokens : 8; /**< UINT */
unsigned Padding : 19;
unsigned Extended : 1; /**< BOOL */
unsigned Padding : 20;
};
enum tgsi_file_type {
@ -117,8 +110,7 @@ struct tgsi_declaration
unsigned Semantic : 1; /**< BOOL, any semantic info? */
unsigned Centroid : 1; /**< centroid sampling? */
unsigned Invariant : 1; /**< invariant optimization? */
unsigned Padding : 4;
unsigned Extended : 1; /**< BOOL */
unsigned Padding : 5;
};
struct tgsi_declaration_range
@ -139,8 +131,8 @@ struct tgsi_declaration_range
struct tgsi_declaration_semantic
{
unsigned SemanticName : 8; /**< one of TGSI_SEMANTIC_x */
unsigned SemanticIndex : 16; /**< UINT */
unsigned Name : 8; /**< one of TGSI_SEMANTIC_x */
unsigned Index : 16; /**< UINT */
unsigned Padding : 8;
};
@ -151,8 +143,7 @@ struct tgsi_immediate
unsigned Type : 4; /**< TGSI_TOKEN_TYPE_IMMEDIATE */
unsigned NrTokens : 8; /**< UINT */
unsigned DataType : 4; /**< one of TGSI_IMM_x */
unsigned Padding : 15;
unsigned Extended : 1; /**< BOOL */
unsigned Padding : 16;
};
union tgsi_immediate_data
@ -295,8 +286,6 @@ union tgsi_immediate_data
*
* If Predicate is TRUE, tgsi_instruction_predicate token immediately follows.
*
* If Extended is TRUE, it is now executed.
*
* Saturate controls how are final results in destination registers modified.
*/
@ -309,12 +298,15 @@ struct tgsi_instruction
unsigned NumDstRegs : 2; /* UINT */
unsigned NumSrcRegs : 4; /* UINT */
unsigned Predicate : 1; /* BOOL */
unsigned Padding : 2;
unsigned Extended : 1; /* BOOL */
unsigned Label : 1;
unsigned Texture : 1;
unsigned Padding : 1;
};
/*
* If tgsi_instruction::Extended is TRUE, tgsi_instruction_ext follows.
* If tgsi_instruction::Label is TRUE, tgsi_instruction_label follows.
*
* If tgsi_instruction::Texture is TRUE, tgsi_instruction_texture follows.
*
* Then, tgsi_instruction::NumDstRegs of tgsi_dst_register follow.
*
@ -324,38 +316,15 @@ struct tgsi_instruction
* instruction, including the instruction word.
*/
#define TGSI_INSTRUCTION_EXT_TYPE_LABEL 1
#define TGSI_INSTRUCTION_EXT_TYPE_TEXTURE 2
struct tgsi_instruction_ext
{
unsigned Type : 4; /* TGSI_INSTRUCTION_EXT_TYPE_ */
unsigned Padding : 27;
unsigned Extended : 1; /* BOOL */
};
/*
* If tgsi_instruction_ext::Type is TGSI_INSTRUCTION_EXT_TYPE_LABEL, it
* should be cast to tgsi_instruction_ext_label.
*
* If tgsi_instruction_ext::Type is TGSI_INSTRUCTION_EXT_TYPE_TEXTURE, it
* should be cast to tgsi_instruction_ext_texture.
*
* If tgsi_instruction_ext::Extended is TRUE, another tgsi_instruction_ext
* follows.
*/
#define TGSI_SWIZZLE_X 0
#define TGSI_SWIZZLE_Y 1
#define TGSI_SWIZZLE_Z 2
#define TGSI_SWIZZLE_W 3
struct tgsi_instruction_ext_label
struct tgsi_instruction_label
{
unsigned Type : 4; /* TGSI_INSTRUCTION_EXT_TYPE_LABEL */
unsigned Label : 24; /* UINT */
unsigned Padding : 3;
unsigned Extended : 1; /* BOOL */
unsigned Padding : 8;
};
#define TGSI_TEXTURE_UNKNOWN 0
@ -369,12 +338,10 @@ struct tgsi_instruction_ext_label
#define TGSI_TEXTURE_SHADOWRECT 8
#define TGSI_TEXTURE_COUNT 9
struct tgsi_instruction_ext_texture
struct tgsi_instruction_texture
{
unsigned Type : 4; /* TGSI_INSTRUCTION_EXT_TYPE_TEXTURE */
unsigned Texture : 8; /* TGSI_TEXTURE_ */
unsigned Padding : 19;
unsigned Extended : 1; /* BOOL */
unsigned Padding : 24;
};
/*
@ -406,26 +373,24 @@ struct tgsi_instruction_predicate
* The fetched register components are swizzled according to SwizzleX, SwizzleY,
* SwizzleZ and SwizzleW.
*
* If Extended is TRUE, any further modifications to the source register are
* made to this temporary storage.
*/
struct tgsi_src_register
{
unsigned File : 4; /* TGSI_FILE_ */
unsigned Indirect : 1; /* BOOL */
unsigned Dimension : 1; /* BOOL */
int Index : 16; /* SINT */
unsigned SwizzleX : 2; /* TGSI_SWIZZLE_ */
unsigned SwizzleY : 2; /* TGSI_SWIZZLE_ */
unsigned SwizzleZ : 2; /* TGSI_SWIZZLE_ */
unsigned SwizzleW : 2; /* TGSI_SWIZZLE_ */
unsigned Negate : 1; /* BOOL */
unsigned Indirect : 1; /* BOOL */
unsigned Dimension : 1; /* BOOL */
int Index : 16; /* SINT */
unsigned Extended : 1; /* BOOL */
unsigned Absolute : 1; /* BOOL */
unsigned Negate : 1; /* BOOL */
};
/**
* If tgsi_src_register::Extended is TRUE, tgsi_src_register_ext follows.
* If tgsi_src_register::Modifier is TRUE, tgsi_src_register_modifier follows.
*
* Then, if tgsi_src_register::Indirect is TRUE, another tgsi_src_register
* follows.
@ -433,58 +398,13 @@ struct tgsi_src_register
* Then, if tgsi_src_register::Dimension is TRUE, tgsi_dimension follows.
*/
#define TGSI_SRC_REGISTER_EXT_TYPE_MOD 1
struct tgsi_src_register_ext
{
unsigned Type : 4; /* TGSI_SRC_REGISTER_EXT_TYPE_ */
unsigned Padding : 27;
unsigned Extended : 1; /* BOOL */
};
/**
* If tgsi_src_register_ext::Type is TGSI_SRC_REGISTER_EXT_TYPE_MOD,
* it should be cast to tgsi_src_register_ext_mod.
*
* If tgsi_dst_register_ext::Extended is TRUE, another tgsi_dst_register_ext
* follows.
*/
/**
* Extra src register modifiers
*
* If Complement is TRUE, the source register is modified by subtracting it
* from 1.0.
*
* If Bias is TRUE, the source register is modified by subtracting 0.5 from it.
*
* If Scale2X is TRUE, the source register is modified by multiplying it by 2.0.
*
* If Absolute is TRUE, the source register is modified by removing the sign.
*
* If Negate is TRUE, the source register is modified by negating it.
*/
struct tgsi_src_register_ext_mod
{
unsigned Type : 4; /* TGSI_SRC_REGISTER_EXT_TYPE_MOD */
unsigned Complement : 1; /* BOOL */
unsigned Bias : 1; /* BOOL */
unsigned Scale2X : 1; /* BOOL */
unsigned Absolute : 1; /* BOOL */
unsigned Negate : 1; /* BOOL */
unsigned Padding : 22;
unsigned Extended : 1; /* BOOL */
};
struct tgsi_dimension
{
unsigned Indirect : 1; /* BOOL */
unsigned Dimension : 1; /* BOOL */
unsigned Padding : 13;
unsigned Padding : 14;
int Index : 16; /* SINT */
unsigned Extended : 1; /* BOOL */
};
struct tgsi_dst_register
@ -494,51 +414,9 @@ struct tgsi_dst_register
unsigned Indirect : 1; /* BOOL */
unsigned Dimension : 1; /* BOOL */
int Index : 16; /* SINT */
unsigned Padding : 5;
unsigned Extended : 1; /* BOOL */
unsigned Padding : 6;
};
/*
* If tgsi_dst_register::Extended is TRUE, tgsi_dst_register_ext follows.
*
* Then, if tgsi_dst_register::Indirect is TRUE, tgsi_src_register follows.
*/
#define TGSI_DST_REGISTER_EXT_TYPE_MODULATE 1
struct tgsi_dst_register_ext
{
unsigned Type : 4; /* TGSI_DST_REGISTER_EXT_TYPE_ */
unsigned Padding : 27;
unsigned Extended : 1; /* BOOL */
};
/**
* Extra destination register modifiers
*
* If tgsi_dst_register_ext::Type is TGSI_DST_REGISTER_EXT_TYPE_MODULATE,
* it should be cast to tgsi_dst_register_ext_modulate.
*
* If tgsi_dst_register_ext::Extended is TRUE, another tgsi_dst_register_ext
* follows.
*/
#define TGSI_MODULATE_1X 0
#define TGSI_MODULATE_2X 1
#define TGSI_MODULATE_4X 2
#define TGSI_MODULATE_8X 3
#define TGSI_MODULATE_HALF 4
#define TGSI_MODULATE_QUARTER 5
#define TGSI_MODULATE_EIGHTH 6
#define TGSI_MODULATE_COUNT 7
struct tgsi_dst_register_ext_modulate
{
unsigned Type : 4; /* TGSI_DST_REGISTER_EXT_TYPE_MODULATE */
unsigned Modulate : 4; /* TGSI_MODULATE_ */
unsigned Padding : 23;
unsigned Extended : 1; /* BOOL */
};
#ifdef __cplusplus
}

4
src/gallium/state_trackers/python/samples/tri.py
View file

@ -159,7 +159,7 @@ def test(dev):
# vertex shader
vs = Shader('''
VERT1.1
VERT
DCL IN[0], POSITION, CONSTANT
DCL IN[1], COLOR, CONSTANT
DCL OUT[0], POSITION, CONSTANT
@ -172,7 +172,7 @@ def test(dev):
# fragment shader
fs = Shader('''
FRAG1.1
FRAG
DCL IN[0], COLOR, LINEAR
DCL OUT[0], COLOR, CONSTANT
0:MOV OUT[0], IN[0]

2
src/gallium/state_trackers/python/tests/regress/fragment-shader/frag-abs.sh
View file

@ -1,4 +1,4 @@
FRAG1.1
FRAG
DCL IN[0], COLOR, LINEAR
DCL OUT[0], COLOR

2
src/gallium/state_trackers/python/tests/regress/fragment-shader/frag-add.sh
View file

@ -1,4 +1,4 @@
FRAG1.1
FRAG
DCL IN[0], COLOR, LINEAR
DCL OUT[0], COLOR

2
src/gallium/state_trackers/python/tests/regress/fragment-shader/frag-dp3.sh
View file

@ -1,4 +1,4 @@
FRAG1.1
FRAG
DCL IN[0], COLOR, LINEAR
DCL OUT[0], COLOR

2
src/gallium/state_trackers/python/tests/regress/fragment-shader/frag-dp4.sh
View file

@ -1,4 +1,4 @@
FRAG1.1
FRAG
DCL IN[0], COLOR, LINEAR
DCL OUT[0], COLOR

2
src/gallium/state_trackers/python/tests/regress/fragment-shader/frag-dst.sh
View file

@ -1,4 +1,4 @@
FRAG1.1
FRAG
DCL IN[0], COLOR, LINEAR
DCL OUT[0], COLOR

2
src/gallium/state_trackers/python/tests/regress/fragment-shader/frag-ex2.sh
View file

@ -1,4 +1,4 @@
FRAG1.1
FRAG
DCL IN[0], COLOR, LINEAR
DCL OUT[0], COLOR

2
src/gallium/state_trackers/python/tests/regress/fragment-shader/frag-flr.sh
View file

@ -1,4 +1,4 @@
FRAG1.1
FRAG
DCL IN[0], COLOR, LINEAR
DCL OUT[0], COLOR

2
src/gallium/state_trackers/python/tests/regress/fragment-shader/frag-frc.sh
View file

@ -1,4 +1,4 @@
FRAG1.1
FRAG
DCL IN[0], COLOR, LINEAR
DCL OUT[0], COLOR

2
src/gallium/state_trackers/python/tests/regress/fragment-shader/frag-lg2.sh
View file

@ -1,4 +1,4 @@
FRAG1.1
FRAG
DCL IN[0], COLOR, LINEAR
DCL OUT[0], COLOR

2
src/gallium/state_trackers/python/tests/regress/fragment-shader/frag-lit.sh
View file

@ -1,4 +1,4 @@
FRAG1.1
FRAG
DCL IN[0], COLOR, LINEAR
DCL OUT[0], COLOR

2
src/gallium/state_trackers/python/tests/regress/fragment-shader/frag-lrp.sh
View file

@ -1,4 +1,4 @@
FRAG1.1
FRAG
DCL IN[0], COLOR, LINEAR
DCL OUT[0], COLOR

2
src/gallium/state_trackers/python/tests/regress/fragment-shader/frag-mad.sh
View file

@ -1,4 +1,4 @@
FRAG1.1
FRAG
DCL IN[0], COLOR, LINEAR
DCL OUT[0], COLOR

2
src/gallium/state_trackers/python/tests/regress/fragment-shader/frag-max.sh
View file

@ -1,4 +1,4 @@
FRAG1.1
FRAG
DCL IN[0], COLOR, LINEAR
DCL OUT[0], COLOR

2
src/gallium/state_trackers/python/tests/regress/fragment-shader/frag-min.sh
View file

@ -1,4 +1,4 @@
FRAG1.1
FRAG
DCL IN[0], COLOR, LINEAR
DCL OUT[0], COLOR

2
src/gallium/state_trackers/python/tests/regress/fragment-shader/frag-mov.sh
View file

@ -1,4 +1,4 @@
FRAG1.1
FRAG
DCL IN[0], COLOR, LINEAR
DCL OUT[0], COLOR

2
src/gallium/state_trackers/python/tests/regress/fragment-shader/frag-mul.sh
View file

@ -1,4 +1,4 @@
FRAG1.1
FRAG
DCL IN[0], COLOR, LINEAR
DCL OUT[0], COLOR

2
src/gallium/state_trackers/python/tests/regress/fragment-shader/frag-rcp.sh
View file

@ -1,4 +1,4 @@
FRAG1.1
FRAG
DCL IN[0], COLOR, LINEAR
DCL OUT[0], COLOR

2
src/gallium/state_trackers/python/tests/regress/fragment-shader/frag-rsq.sh
View file

@ -1,4 +1,4 @@
FRAG1.1
FRAG
DCL IN[0], COLOR, LINEAR
DCL OUT[0], COLOR

2
src/gallium/state_trackers/python/tests/regress/fragment-shader/frag-sge.sh
View file

@ -1,4 +1,4 @@
FRAG1.1
FRAG
DCL IN[0], COLOR, LINEAR
DCL OUT[0], COLOR

2
src/gallium/state_trackers/python/tests/regress/fragment-shader/frag-srcmod-abs.sh
View file

@ -1,4 +1,4 @@
FRAG1.1
FRAG
DCL IN[0], COLOR, LINEAR
DCL OUT[0], COLOR

2
src/gallium/state_trackers/python/tests/regress/fragment-shader/frag-srcmod-absneg.sh
View file

@ -1,4 +1,4 @@
FRAG1.1
FRAG
DCL IN[0], COLOR, LINEAR
DCL OUT[0], COLOR

2
src/gallium/state_trackers/python/tests/regress/fragment-shader/frag-srcmod-neg.sh
View file

@ -1,4 +1,4 @@
FRAG1.1
FRAG
DCL IN[0], COLOR, LINEAR
DCL OUT[0], COLOR

2
src/gallium/state_trackers/python/tests/regress/fragment-shader/frag-srcmod-swz.sh
View file

@ -1,4 +1,4 @@
FRAG1.1
FRAG
DCL IN[0], COLOR, LINEAR
DCL OUT[0], COLOR

2
src/gallium/state_trackers/python/tests/regress/fragment-shader/frag-sub.sh
View file

@ -1,4 +1,4 @@
FRAG1.1
FRAG
DCL IN[0], COLOR, LINEAR
DCL OUT[0], COLOR

2
src/gallium/state_trackers/python/tests/regress/fragment-shader/frag-xpd.sh
View file

@ -1,4 +1,4 @@
FRAG1.1
FRAG
DCL IN[0], COLOR, LINEAR
DCL OUT[0], COLOR

2
src/gallium/state_trackers/python/tests/regress/fragment-shader/fragment-shader.py
View file

@ -131,7 +131,7 @@ def test(dev, name):
# vertex shader
vs = Shader('''
VERT1.1
VERT
DCL IN[0], POSITION
DCL IN[1], COLOR
DCL OUT[0], POSITION

2
src/gallium/state_trackers/python/tests/regress/vertex-shader/vert-abs.sh
View file

@ -1,4 +1,4 @@
VERT1.1
VERT
DCL IN[0], POSITION
DCL IN[1], COLOR

2
src/gallium/state_trackers/python/tests/regress/vertex-shader/vert-add.sh
View file

@ -1,4 +1,4 @@
VERT1.1
VERT
DCL IN[0], POSITION
DCL IN[1], COLOR

2
src/gallium/state_trackers/python/tests/regress/vertex-shader/vert-arl.sh
View file

@ -1,4 +1,4 @@
VERT1.1
VERT
DCL IN[0], POSITION
DCL OUT[0], POSITION

2
src/gallium/state_trackers/python/tests/regress/vertex-shader/vert-arr.sh
View file

@ -1,4 +1,4 @@
VERT1.1
VERT
DCL IN[0], POSITION
DCL OUT[0], POSITION

2
src/gallium/state_trackers/python/tests/regress/vertex-shader/vert-dp3.sh
View file

@ -1,4 +1,4 @@
VERT1.1
VERT
DCL IN[0], POSITION
DCL IN[1], COLOR

2
src/gallium/state_trackers/python/tests/regress/vertex-shader/vert-dp4.sh
View file

@ -1,4 +1,4 @@
VERT1.1
VERT
DCL IN[0], POSITION
DCL IN[1], COLOR

2
src/gallium/state_trackers/python/tests/regress/vertex-shader/vert-dst.sh
View file

@ -1,4 +1,4 @@
VERT1.1
VERT
DCL IN[0], POSITION
DCL IN[1], COLOR

2
src/gallium/state_trackers/python/tests/regress/vertex-shader/vert-ex2.sh
View file

@ -1,4 +1,4 @@
VERT1.1
VERT
DCL IN[0], POSITION
DCL IN[1], COLOR

2
src/gallium/state_trackers/python/tests/regress/vertex-shader/vert-flr.sh
View file

@ -1,4 +1,4 @@
VERT1.1
VERT
DCL IN[0], POSITION
DCL OUT[0], POSITION

2
src/gallium/state_trackers/python/tests/regress/vertex-shader/vert-frc.sh
View file

@ -1,4 +1,4 @@
VERT1.1
VERT
DCL IN[0], POSITION
DCL OUT[0], POSITION

2
src/gallium/state_trackers/python/tests/regress/vertex-shader/vert-lg2.sh
View file

@ -1,4 +1,4 @@
VERT1.1
VERT
DCL IN[0], POSITION
DCL IN[1], COLOR

2
src/gallium/state_trackers/python/tests/regress/vertex-shader/vert-lit.sh
View file

@ -1,4 +1,4 @@
VERT1.1
VERT
DCL IN[0], POSITION
DCL IN[1], COLOR

2
src/gallium/state_trackers/python/tests/regress/vertex-shader/vert-lrp.sh
View file

@ -1,4 +1,4 @@
VERT1.1
VERT
DCL IN[0], POSITION
DCL IN[1], COLOR

2
src/gallium/state_trackers/python/tests/regress/vertex-shader/vert-mad.sh
View file

@ -1,4 +1,4 @@
VERT1.1
VERT
DCL IN[0], POSITION
DCL IN[1], COLOR

2
src/gallium/state_trackers/python/tests/regress/vertex-shader/vert-max.sh
View file

@ -1,4 +1,4 @@
VERT1.1
VERT
DCL IN[0], POSITION
DCL IN[1], COLOR

2
src/gallium/state_trackers/python/tests/regress/vertex-shader/vert-min.sh
View file

@ -1,4 +1,4 @@
VERT1.1
VERT
DCL IN[0], POSITION
DCL IN[1], COLOR

2
src/gallium/state_trackers/python/tests/regress/vertex-shader/vert-mov.sh
View file

@ -1,4 +1,4 @@
VERT1.1
VERT
DCL IN[0], POSITION
DCL IN[1], COLOR

2
src/gallium/state_trackers/python/tests/regress/vertex-shader/vert-mul.sh
View file

@ -1,4 +1,4 @@
VERT1.1
VERT
DCL IN[0], POSITION
DCL IN[1], COLOR

2
src/gallium/state_trackers/python/tests/regress/vertex-shader/vert-rcp.sh
View file

@ -1,4 +1,4 @@
VERT1.1
VERT
DCL IN[0], POSITION
DCL IN[1], COLOR

2
src/gallium/state_trackers/python/tests/regress/vertex-shader/vert-rsq.sh
View file

@ -1,4 +1,4 @@
VERT1.1
VERT
DCL IN[0], POSITION
DCL IN[1], COLOR

2
src/gallium/state_trackers/python/tests/regress/vertex-shader/vert-sge.sh
View file

@ -1,4 +1,4 @@
VERT1.1
VERT
DCL IN[0], POSITION
DCL IN[1], COLOR

2
src/gallium/state_trackers/python/tests/regress/vertex-shader/vert-slt.sh
View file

@ -1,4 +1,4 @@
VERT1.1
VERT
DCL IN[0], POSITION
DCL IN[1], COLOR

2
src/gallium/state_trackers/python/tests/regress/vertex-shader/vert-srcmod-abs.sh
View file

@ -1,4 +1,4 @@
VERT1.1
VERT
DCL IN[0], POSITION
DCL IN[1], COLOR

2
src/gallium/state_trackers/python/tests/regress/vertex-shader/vert-srcmod-absneg.sh
View file

@ -1,4 +1,4 @@
VERT1.1
VERT
DCL IN[0], POSITION
DCL IN[1], COLOR

2
src/gallium/state_trackers/python/tests/regress/vertex-shader/vert-srcmod-neg.sh
View file

@ -1,4 +1,4 @@
VERT1.1
VERT
DCL IN[0], POSITION
DCL IN[1], COLOR

2
src/gallium/state_trackers/python/tests/regress/vertex-shader/vert-srcmod-swz.sh
View file

@ -1,4 +1,4 @@
VERT1.1
VERT
DCL IN[0], POSITION
DCL IN[1], COLOR

2
src/gallium/state_trackers/python/tests/regress/vertex-shader/vert-sub.sh
View file

@ -1,4 +1,4 @@
VERT1.1
VERT
DCL IN[0], POSITION
DCL IN[1], COLOR

2
src/gallium/state_trackers/python/tests/regress/vertex-shader/vert-xpd.sh
View file

@ -1,4 +1,4 @@
VERT1.1
VERT
DCL IN[0], POSITION
DCL IN[1], COLOR

2
src/gallium/state_trackers/python/tests/regress/vertex-shader/vertex-shader.py
View file

@ -135,7 +135,7 @@ def test(dev, name):
# fragment shader
fs = Shader('''
FRAG1.1
FRAG
DCL IN[0], COLOR, LINEAR
DCL OUT[0], COLOR, CONSTANT
0:MOV OUT[0], IN[0]

4
src/gallium/state_trackers/python/tests/texture_render.py
View file

@ -171,7 +171,7 @@ class TextureTest(TestCase):
# vertex shader
vs = Shader('''
VERT1.1
VERT
DCL IN[0], POSITION, CONSTANT
DCL IN[1], GENERIC, CONSTANT
DCL OUT[0], POSITION, CONSTANT
@ -185,7 +185,7 @@ class TextureTest(TestCase):
# fragment shader
fs = Shader('''
FRAG1.1
FRAG
DCL IN[0], GENERIC[0], LINEAR
DCL OUT[0], COLOR, CONSTANT
DCL SAMP[0], CONSTANT

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