intel: Track stencil aux usage on Gen12+

Enable stencil compression enable and control surface enable bit if
stencil buffer lossless compression is enabled.

v2: Remove unnecessary GEN_GEN check (Nanley Chery)

v3: (Nanley Chery)
- Change commit subject tag from intel/isl to intel
- Keep assignment order correct

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
This commit is contained in:
Sagar Ghuge 2019-10-23 16:24:46 -07:00
parent 53d472df24
commit c401186762
4 changed files with 10 additions and 0 deletions

View file

@ -2993,6 +2993,7 @@ iris_set_framebuffer_state(struct pipe_context *ctx,
if (stencil_res) {
view.usage |= ISL_SURF_USAGE_STENCIL_BIT;
info.stencil_aux_usage = stencil_res->aux.usage;
info.stencil_surf = &stencil_res->surf;
info.stencil_address = stencil_res->bo->gtt_offset + stencil_res->offset;
if (!zres) {

View file

@ -1600,6 +1600,7 @@ blorp_emit_depth_stencil_config(struct blorp_batch *batch,
if (params->stencil.enabled) {
info.stencil_surf = &params->stencil.surf;
info.stencil_aux_usage = params->stencil.aux_usage;
struct blorp_address stencil_address = params->stencil.addr;
#if GEN_GEN == 6
/* Sandy bridge hardware does not technically support mipmapped stencil.

View file

@ -1445,6 +1445,11 @@ struct isl_depth_stencil_hiz_emit_info {
* The depth clear value
*/
float depth_clear_value;
/**
* Track stencil aux usage for Gen >= 12
*/
enum isl_aux_usage stencil_aux_usage;
};
extern const struct isl_format_layout isl_format_layouts[];

View file

@ -146,6 +146,9 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
sb.Depth = sb.RenderTargetViewExtent = info->view->array_len - 1;
sb.SurfLOD = info->view->base_level;
sb.MinimumArrayElement = info->view->base_array_layer;
sb.StencilCompressionEnable =
info->stencil_aux_usage == ISL_AUX_USAGE_CCS_E;
sb.ControlSurfaceEnable = sb.StencilCompressionEnable;
#elif GEN_GEN >= 8 || GEN_IS_HASWELL
sb.StencilBufferEnable = true;
#endif