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radeonsi/gfx11: fix the CU_EN clear mask for RSRC4_GS

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Fixes: 9fecac091f - radeonsi/gfx11: scattered register deltas

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
(cherry picked from commit 31438fbab5)
This commit is contained in:
Marek Olšák 2023-02-05 00:13:50 -05:00 • committed by Eric Engestrom
parent 269a94eef7
commit 87c167e2f4
2 changed files with 3 additions and 2 deletions
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2
.pick_status.json
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@ -6232,7 +6232,7 @@
"description": "radeonsi/gfx11: fix the CU_EN clear mask for RSRC4_GS",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": "9fecac091f3159eb50a3e3dea2312218bb87d8c1"
},

3
src/gallium/drivers/radeonsi/si_state_shaders.cpp
View file

@ -1234,7 +1234,8 @@ static void gfx10_emit_shader_ngg_tail(struct si_context *sctx, struct si_shader
(sctx->gfx_level >= GFX10 ? radeon_set_sh_reg_idx3_func : radeon_set_sh_reg_func));
ac_set_reg_cu_en(&sctx->gfx_cs, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
shader->ctx_reg.ngg.spi_shader_pgm_rsrc4_gs,
C_00B204_CU_EN_GFX10, 16, &sctx->screen->info,
sctx->gfx_level >= GFX11 ? C_00B204_CU_EN_GFX11 : C_00B204_CU_EN_GFX10, 16,
&sctx->screen->info,
(void (*)(void*, unsigned, uint32_t))
(sctx->gfx_level >= GFX10 ? radeon_set_sh_reg_idx3_func : radeon_set_sh_reg_func));
sctx->tracked_regs.reg_saved &= ~BITFIELD64_BIT(SI_TRACKED_SPI_SHADER_PGM_RSRC4_GS) &