From 874bc0953772eee519c48052cc81eb211917f09c Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Fri, 3 Oct 2025 11:28:13 +0200 Subject: [PATCH] radv: reserve more CS space when executing DGC calls This can trigger an assert otherwise. The space reserved before executing DGC IBs is an arbitrary number which should be large enough in all cases. Found this while implementing descriptor heap. Cc: mesa-stable Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_cmd_buffer.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 2ec10505676..d8fa842fd95 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -12897,6 +12897,8 @@ radv_dgc_execute_ib(struct radv_cmd_buffer *cmd_buffer, const VkGeneratedCommand const uint64_t main_trailer_va = ib_va + radv_get_indirect_main_trailer_offset(pGeneratedCommandsInfo); struct radv_cmd_stream *cs = cmd_buffer->cs; + radeon_check_space(device->ws, cs->b, 64); + device->ws->cs_chain_dgc_ib(cs->b, main_ib_va, cmdbuf_size >> 2, main_trailer_va, cmd_buffer->state.predicating); if (task_shader) { @@ -13012,6 +13014,8 @@ radv_CmdExecuteGeneratedCommandsEXT(VkCommandBuffer commandBuffer, VkBool32 isPr } if (!radv_cmd_buffer_uses_mec(cmd_buffer)) { + radeon_check_space(device->ws, cs->b, 2); + radeon_begin(cs); radeon_emit(PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating)); radeon_emit(0);