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freedreno/regs: Define unknown SP_FS_PREFETCH_CNTL fields

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Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24433>
This commit is contained in:
Danylo Piliaiev 2023-08-02 13:57:12 +02:00 • committed by Marge Bot
parent 6aabdb7a57
commit 86440685f3
6 changed files with 25 additions and 32 deletions
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4
src/freedreno/.gitlab-ci/reference/crash.log
View file

@ -7166,7 +7166,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_FS_MRT[0x5].REG: { COLOR_FORMAT = 0 }
00000000 SP_FS_MRT[0x6].REG: { COLOR_FORMAT = 0 }
00000000 SP_FS_MRT[0x7].REG: { COLOR_FORMAT = 0 }
00000000 SP_FS_PREFETCH_CNTL: { COUNT = 0 }
00000000 SP_FS_PREFETCH_CNTL: { COUNT = 0 | CONSTSLOTID = 0 }
03c00000 SP_FS_PREFETCH[0].CMD: { SRC = 0 | SAMP_ID = 0 | TEX_ID = 0 | DST = r0.x | WRMASK = 0xf | CMD = TEX_PREFETCH_UNK0 }
03c00000 SP_FS_PREFETCH[0x1].CMD: { SRC = 0 | SAMP_ID = 0 | TEX_ID = 0 | DST = r0.x | WRMASK = 0xf | CMD = TEX_PREFETCH_UNK0 }
03c00000 SP_FS_PREFETCH[0x2].CMD: { SRC = 0 | SAMP_ID = 0 | TEX_ID = 0 | DST = r0.x | WRMASK = 0xf | CMD = TEX_PREFETCH_UNK0 }
@ -7234,7 +7234,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_FS_MRT[0x5].REG: { COLOR_FORMAT = 0 }
00000000 SP_FS_MRT[0x6].REG: { COLOR_FORMAT = 0 }
00000000 SP_FS_MRT[0x7].REG: { COLOR_FORMAT = 0 }
00000000 SP_FS_PREFETCH_CNTL: { COUNT = 0 }
00000000 SP_FS_PREFETCH_CNTL: { COUNT = 0 | CONSTSLOTID = 0 }
03c00000 SP_FS_PREFETCH[0].CMD: { SRC = 0 | SAMP_ID = 0 | TEX_ID = 0 | DST = r0.x | WRMASK = 0xf | CMD = TEX_PREFETCH_UNK0 }
03c00000 SP_FS_PREFETCH[0x1].CMD: { SRC = 0 | SAMP_ID = 0 | TEX_ID = 0 | DST = r0.x | WRMASK = 0xf | CMD = TEX_PREFETCH_UNK0 }
03c00000 SP_FS_PREFETCH[0x2].CMD: { SRC = 0 | SAMP_ID = 0 | TEX_ID = 0 | DST = r0.x | WRMASK = 0xf | CMD = TEX_PREFETCH_UNK0 }

12
src/freedreno/.gitlab-ci/reference/crash_prefetch.log
View file

@ -2987,7 +2987,7 @@ got cmdszdw=83
!+ 0000000e SP_FS_MRT[0x1].REG: { COLOR_FORMAT = FMT6_5_6_5_UNORM }
!+ 00000060 SP_FS_MRT[0x2].REG: { COLOR_FORMAT = FMT6_16_16_16_16_UNORM }
!+ 0000000e SP_FS_MRT[0x3].REG: { COLOR_FORMAT = FMT6_5_6_5_UNORM }
!+ 00007fc0 SP_FS_PREFETCH_CNTL: { COUNT = 0 | UNK6 = 0x1ff }
!+ 00007fc0 SP_FS_PREFETCH_CNTL: { COUNT = 0 | CONSTSLOTID = 511 }
+ 00000000 SP_FS_PVT_MEM_HW_STACK_OFFSET: { OFFSET = 0 }
+ 00000005 SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | ISAMMODE = ISAMMODE_GL }
!+ 00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
@ -3701,7 +3701,7 @@ got cmdszdw=83
!+ 00000060 SP_FS_MRT[0x1].REG: { COLOR_FORMAT = FMT6_16_16_16_16_UNORM }
!+ 0000000e SP_FS_MRT[0x2].REG: { COLOR_FORMAT = FMT6_5_6_5_UNORM }
!+ 00000043 SP_FS_MRT[0x3].REG: { COLOR_FORMAT = FMT6_16_16_UNORM }
+ 00007fc0 SP_FS_PREFETCH_CNTL: { COUNT = 0 | UNK6 = 0x1ff }
+ 00007fc0 SP_FS_PREFETCH_CNTL: { COUNT = 0 | CONSTSLOTID = 511 }
+ 00000000 SP_FS_PVT_MEM_HW_STACK_OFFSET: { OFFSET = 0 }
+ 00000005 SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | ISAMMODE = ISAMMODE_GL }
+ 00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
@ -4426,7 +4426,7 @@ got cmdszdw=83
!+ 0000000e SP_FS_MRT[0x1].REG: { COLOR_FORMAT = FMT6_5_6_5_UNORM }
!+ 00000043 SP_FS_MRT[0x2].REG: { COLOR_FORMAT = FMT6_16_16_UNORM }
!+ 00000061 SP_FS_MRT[0x3].REG: { COLOR_FORMAT = FMT6_16_16_16_16_SNORM }
+ 00007fc0 SP_FS_PREFETCH_CNTL: { COUNT = 0 | UNK6 = 0x1ff }
+ 00007fc0 SP_FS_PREFETCH_CNTL: { COUNT = 0 | CONSTSLOTID = 511 }
+ 00000000 SP_FS_PVT_MEM_HW_STACK_OFFSET: { OFFSET = 0 }
+ 00000005 SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | ISAMMODE = ISAMMODE_GL }
+ 00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
@ -5077,7 +5077,7 @@ ESTIMATED CRASH LOCATION!
!+ 00000043 SP_FS_MRT[0x1].REG: { COLOR_FORMAT = FMT6_16_16_UNORM }
!+ 00000061 SP_FS_MRT[0x2].REG: { COLOR_FORMAT = FMT6_16_16_16_16_SNORM }
!+ 0000024b SP_FS_MRT[0x3].REG: { COLOR_FORMAT = FMT6_32_UINT | COLOR_UINT }
+ 00007fc0 SP_FS_PREFETCH_CNTL: { COUNT = 0 | UNK6 = 0x1ff }
+ 00007fc0 SP_FS_PREFETCH_CNTL: { COUNT = 0 | CONSTSLOTID = 511 }
+ 00000000 SP_FS_PVT_MEM_HW_STACK_OFFSET: { OFFSET = 0 }
+ 00000005 SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | ISAMMODE = ISAMMODE_GL }
+ 00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
@ -18994,7 +18994,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_FS_MRT[0x5].REG: { COLOR_FORMAT = 0 }
00000000 SP_FS_MRT[0x6].REG: { COLOR_FORMAT = 0 }
00000000 SP_FS_MRT[0x7].REG: { COLOR_FORMAT = 0 }
00007fc0 SP_FS_PREFETCH_CNTL: { COUNT = 0 | UNK6 = 0x1ff }
00007fc0 SP_FS_PREFETCH_CNTL: { COUNT = 0 | CONSTSLOTID = 511 }
03c00000 SP_FS_PREFETCH[0].CMD: { SRC = 0 | SAMP_ID = 0 | TEX_ID = 0 | DST = r0.x | WRMASK = 0xf | CMD = TEX_PREFETCH_UNK0 }
03c00000 SP_FS_PREFETCH[0x1].CMD: { SRC = 0 | SAMP_ID = 0 | TEX_ID = 0 | DST = r0.x | WRMASK = 0xf | CMD = TEX_PREFETCH_UNK0 }
03c00000 SP_FS_PREFETCH[0x2].CMD: { SRC = 0 | SAMP_ID = 0 | TEX_ID = 0 | DST = r0.x | WRMASK = 0xf | CMD = TEX_PREFETCH_UNK0 }
@ -19062,7 +19062,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_FS_MRT[0x5].REG: { COLOR_FORMAT = 0 }
00000000 SP_FS_MRT[0x6].REG: { COLOR_FORMAT = 0 }
00000000 SP_FS_MRT[0x7].REG: { COLOR_FORMAT = 0 }
00007fc0 SP_FS_PREFETCH_CNTL: { COUNT = 0 | UNK6 = 0x1ff }
00007fc0 SP_FS_PREFETCH_CNTL: { COUNT = 0 | CONSTSLOTID = 511 }
03c00000 SP_FS_PREFETCH[0].CMD: { SRC = 0 | SAMP_ID = 0 | TEX_ID = 0 | DST = r0.x | WRMASK = 0xf | CMD = TEX_PREFETCH_UNK0 }
03c00000 SP_FS_PREFETCH[0x1].CMD: { SRC = 0 | SAMP_ID = 0 | TEX_ID = 0 | DST = r0.x | WRMASK = 0xf | CMD = TEX_PREFETCH_UNK0 }
03c00000 SP_FS_PREFETCH[0x2].CMD: { SRC = 0 | SAMP_ID = 0 | TEX_ID = 0 | DST = r0.x | WRMASK = 0xf | CMD = TEX_PREFETCH_UNK0 }

4
src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log
View file

@ -973,7 +973,7 @@ cmdstream[0]: 265 dwords
0000000001054320: 0000: 48920808 00000000 00000000 00000000 00000000 00000000 00000000 00000000
*
write SP_FS_PREFETCH_CNTL (a99e)
SP_FS_PREFETCH_CNTL: { COUNT = 0 | UNK6 = 0x1ff }
SP_FS_PREFETCH_CNTL: { COUNT = 0 | CONSTSLOTID = 511 }
0000000001054344: 0000: 40a99e01 00007fc0
write HLSQ_CONTROL_1_REG (b982)
HLSQ_CONTROL_1_REG: { PRIMALLOCTHRESHOLD = 7 }
@ -1483,7 +1483,7 @@ cmdstream[0]: 265 dwords
!+ 000000fc SP_FS_OUTPUT[0x6].REG: { REGID = r63.x }
!+ 000000fc SP_FS_OUTPUT[0x7].REG: { REGID = r63.x }
!+ 00000030 SP_FS_MRT[0].REG: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM }
!+ 00007fc0 SP_FS_PREFETCH_CNTL: { COUNT = 0 | UNK6 = 0x1ff }
!+ 00007fc0 SP_FS_PREFETCH_CNTL: { COUNT = 0 | CONSTSLOTID = 511 }
+ 00000000 SP_CS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
!+ 00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
!+ 00000001 SP_FS_INSTRLEN: 1

8
src/freedreno/.gitlab-ci/reference/fd-clouds.log
View file

@ -600,7 +600,7 @@ cmdstream[0]: 1023 dwords
SP_HS_OBJ_FIRST_EXEC_OFFSET: 0
0000000001121000: 0000: 40a83301 00000000
write SP_FS_PREFETCH_CNTL (a99e)
SP_FS_PREFETCH_CNTL: { COUNT = 0 | UNK6 = 0x1ff }
SP_FS_PREFETCH_CNTL: { COUNT = 0 | CONSTSLOTID = 511 }
0000000001121008: 0000: 40a99e01 00007fc0
write SP_UNKNOWN_A9A8 (a9a8)
SP_UNKNOWN_A9A8: 0
@ -1098,7 +1098,7 @@ cmdstream[0]: 1023 dwords
!+ 000000fc SP_FS_OUTPUT[0x6].REG: { REGID = r63.x }
!+ 000000fc SP_FS_OUTPUT[0x7].REG: { REGID = r63.x }
!+ 00000031 SP_FS_MRT[0].REG: { COLOR_FORMAT = FMT6_8_8_8_X8_UNORM }
!+ 00007fc0 SP_FS_PREFETCH_CNTL: { COUNT = 0 | UNK6 = 0x1ff }
!+ 00007fc0 SP_FS_PREFETCH_CNTL: { COUNT = 0 | CONSTSLOTID = 511 }
+ 00000000 SP_UNKNOWN_A9A8: 0
!+ 00000005 SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | ISAMMODE = ISAMMODE_GL }
!+ 00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
@ -1884,7 +1884,7 @@ cmdstream[0]: 1023 dwords
SP_HS_OBJ_FIRST_EXEC_OFFSET: 0
0000000001120000: 0000: 40a83301 00000000
write SP_FS_PREFETCH_CNTL (a99e)
SP_FS_PREFETCH_CNTL: { COUNT = 0 | UNK6 = 0x1ff }
SP_FS_PREFETCH_CNTL: { COUNT = 0 | CONSTSLOTID = 511 }
0000000001120008: 0000: 40a99e01 00007fc0
write SP_UNKNOWN_A9A8 (a9a8)
SP_UNKNOWN_A9A8: 0
@ -6715,7 +6715,7 @@ cmdstream[0]: 1023 dwords
!+ 00000004 SP_FS_OUTPUT[0x5].REG: { REGID = r1.x }
!+ 00000004 SP_FS_OUTPUT[0x6].REG: { REGID = r1.x }
!+ 00000004 SP_FS_OUTPUT[0x7].REG: { REGID = r1.x }
+ 00007fc0 SP_FS_PREFETCH_CNTL: { COUNT = 0 | UNK6 = 0x1ff }
+ 00007fc0 SP_FS_PREFETCH_CNTL: { COUNT = 0 | CONSTSLOTID = 511 }
+ 00000000 SP_UNKNOWN_A9A8: 0
+ 00000005 SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | ISAMMODE = ISAMMODE_GL }
+ 00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }

6
src/freedreno/.gitlab-ci/reference/prefetch-test.log
View file

@ -3285,7 +3285,7 @@ got cmdszdw=438
!+ 000000fc SP_FS_OUTPUT[0x6].REG: { REGID = r63.x }
!+ 000000fc SP_FS_OUTPUT[0x7].REG: { REGID = r63.x }
!+ 00000030 SP_FS_MRT[0].REG: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM }
!+ 00007fc1 SP_FS_PREFETCH_CNTL: { COUNT = 1 | UNK6 = 0x1ff }
!+ 00007fc1 SP_FS_PREFETCH_CNTL: { COUNT = 1 | CONSTSLOTID = 511 }
!+ 25c40000 SP_FS_PREFETCH[0].CMD: { SRC = 0 | SAMP_ID = 0 | TEX_ID = 0 | DST = r1.x | WRMASK = 0x7 | HALF | CMD = TEX_PREFETCH_SAM }
!+ 00000001 SP_FS_TEX_COUNT: 1
+ 00000000 SP_UNKNOWN_A9A8: 0
@ -152973,7 +152973,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_FS_MRT[0x5].REG: { COLOR_FORMAT = 0 }
00000000 SP_FS_MRT[0x6].REG: { COLOR_FORMAT = 0 }
00000000 SP_FS_MRT[0x7].REG: { COLOR_FORMAT = 0 }
00007fc1 SP_FS_PREFETCH_CNTL: { COUNT = 1 | UNK6 = 0x1ff }
00007fc1 SP_FS_PREFETCH_CNTL: { COUNT = 1 | CONSTSLOTID = 511 }
25c40000 SP_FS_PREFETCH[0].CMD: { SRC = 0 | SAMP_ID = 0 | TEX_ID = 0 | DST = r1.x | WRMASK = 0x7 | HALF | CMD = TEX_PREFETCH_SAM }
03c00000 SP_FS_PREFETCH[0x1].CMD: { SRC = 0 | SAMP_ID = 0 | TEX_ID = 0 | DST = r0.x | WRMASK = 0xf | CMD = TEX_PREFETCH_UNK0 }
03c00000 SP_FS_PREFETCH[0x2].CMD: { SRC = 0 | SAMP_ID = 0 | TEX_ID = 0 | DST = r0.x | WRMASK = 0xf | CMD = TEX_PREFETCH_UNK0 }
@ -153041,7 +153041,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_FS_MRT[0x5].REG: { COLOR_FORMAT = 0 }
00000000 SP_FS_MRT[0x6].REG: { COLOR_FORMAT = 0 }
00000000 SP_FS_MRT[0x7].REG: { COLOR_FORMAT = 0 }
00007fc1 SP_FS_PREFETCH_CNTL: { COUNT = 1 | UNK6 = 0x1ff }
00007fc1 SP_FS_PREFETCH_CNTL: { COUNT = 1 | CONSTSLOTID = 511 }
25c40000 SP_FS_PREFETCH[0].CMD: { SRC = 0 | SAMP_ID = 0 | TEX_ID = 0 | DST = r1.x | WRMASK = 0x7 | HALF | CMD = TEX_PREFETCH_SAM }
03c00000 SP_FS_PREFETCH[0x1].CMD: { SRC = 0 | SAMP_ID = 0 | TEX_ID = 0 | DST = r0.x | WRMASK = 0xf | CMD = TEX_PREFETCH_UNK0 }
03c00000 SP_FS_PREFETCH[0x2].CMD: { SRC = 0 | SAMP_ID = 0 | TEX_ID = 0 | DST = r0.x | WRMASK = 0xf | CMD = TEX_PREFETCH_UNK0 }

23
src/freedreno/registers/adreno/a6xx.xml
View file

@ -3584,25 +3584,18 @@ to upconvert to 32b float internally?
<bitfield name="COUNT" low="0" high="2" type="uint"/>
<bitfield name="IJ_WRITE_DISABLE" pos="3" type="boolean"/>
<doc>
Seem to break derivatives when there is a helper invocation
in the quad. Though from tests it doesn't seem to be
"disable helper invocations" flag.
Similar to "(eq)" flag but disables helper invocations
after the texture prefetch.
</doc>
<bitfield name="UNK4" pos="4" type="boolean" />
<bitfield name="ENDOFQUAD" pos="4" type="boolean" />
<doc>
Bypass writing to regs and overwrite output with tex color.
TODO: How does it work with multiple prefetches?
Bypass writing to regs and overwrite output with color from
CONSTSLOTID const regs.
</doc>
<bitfield name="WRITE_COLOR_TO_OUTPUT" pos="5" type="boolean"/>
<doc>
Doesn't seem to be a reg, size doesn't match and it doesn't do
anything observable.
</doc>
<bitfield name="UNK6" low="6" high="14" type="uint"/>
<doc>
Same as UNK6?
</doc>
<bitfield name="UNK16" low="16" high="24" type="uint"/>
<bitfield name="CONSTSLOTID" low="6" high="14" type="uint"/>
<!-- Blob never uses it -->
<bitfield name="CONSTSLOTID4COORD" low="16" high="24" type="uint" variants="A7XX-"/>
</reg32>
<array offset="0xa99f" name="SP_FS_PREFETCH" stride="1" length="4" variants="A6XX" usage="rp_blit">
<reg32 offset="0" name="CMD" variants="A6XX">