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amd,radv,radeonsi: move some GFX12 emit helpers to common code
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38000>
This commit is contained in:
Samuel Pitoiset
Marge Bot
parent
2009815d61
commit
846b707045
3 changed files with 44 additions and 50 deletions
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@ -135,6 +135,36 @@ struct ac_cmdbuf {
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ac_cmdbuf_emit(0); /* unused */ \
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} while (0)
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/* GFX12 generic packet building helpers for PAIRS packets. Don't use these directly. */
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/* Reserved 1 DWORD to emit the packet header when the sequence ends. */
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#define __ac_gfx12_begin_regs(header) uint32_t header = __cs_num++
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/* Set a register unconditionally. */
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#define ac_gfx12_set_reg(reg, value, base_offset) \
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do { \
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ac_cmdbuf_emit(((reg) - (base_offset)) >> 2); \
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ac_cmdbuf_emit(value); \
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} while (0)
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/* End the sequence and emit the packet header. */
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#define __ac_gfx12_end_regs(header, packet) \
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do { \
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if ((header) + 1 == __cs_num) { \
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__cs_num--; /* no registers have been set, back off */ \
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} else { \
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unsigned __dw_count = __cs_num - (header) - 2; \
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__cs_buf[(header)] = PKT3((packet), __dw_count, 0) | PKT3_RESET_FILTER_CAM_S(1); \
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} \
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} while (0)
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/* GFX12 packet building helpers for PAIRS packets. */
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#define ac_gfx12_begin_context_regs() __ac_gfx12_begin_regs(__cs_context_reg_header)
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#define ac_gfx12_set_context_reg(reg, value) ac_gfx12_set_reg(reg, value, SI_CONTEXT_REG_OFFSET)
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#define ac_gfx12_end_context_regs() __ac_gfx12_end_regs(__cs_context_reg_header, PKT3_SET_CONTEXT_REG_PAIRS)
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struct ac_preamble_state {
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uint64_t border_color_va;
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@ -208,16 +208,6 @@ radeon_check_space(struct radeon_winsys *ws, struct ac_cmdbuf *cs, unsigned need
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/* GFX12 generic packet building helpers for PAIRS packets. Don't use these directly. */
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/* Reserved 1 DWORD to emit the packet header when the sequence ends. */
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#define __gfx12_begin_regs(header) uint32_t header = __cs_num++
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/* Set a register unconditionally. */
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#define __gfx12_set_reg(reg, value, base_offset) \
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do { \
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radeon_emit(((reg) - (base_offset)) >> 2); \
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radeon_emit(value); \
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} while (0)
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/* Set 1 context register optimally. */
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#define __gfx12_opt_set_reg(reg, reg_enum, value, base_offset) \
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do { \
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@ -225,7 +215,7 @@ radeon_check_space(struct radeon_winsys *ws, struct ac_cmdbuf *cs, unsigned need
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const uint32_t __value = (value); \
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if (!BITSET_TEST(__tracked_regs->reg_saved_mask, (reg_enum)) || \
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__tracked_regs->reg_value[(reg_enum)] != __value) { \
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__gfx12_set_reg((reg), __value, base_offset); \
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ac_gfx12_set_reg((reg), __value, base_offset); \
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BITSET_SET(__tracked_regs->reg_saved_mask, (reg_enum)); \
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__tracked_regs->reg_value[(reg_enum)] = __value; \
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} \
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@ -238,25 +228,14 @@ radeon_check_space(struct radeon_winsys *ws, struct ac_cmdbuf *cs, unsigned need
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const uint32_t __v1 = (v1), __v2 = (v2); \
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if (!BITSET_TEST_RANGE_INSIDE_WORD(__tracked_regs->reg_saved_mask, (reg_enum), (reg_enum) + 1, 0x3) || \
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__tracked_regs->reg_value[(reg_enum)] != __v1 || __tracked_regs->reg_value[(reg_enum) + 1] != __v2) { \
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__gfx12_set_reg((reg), __v1, base_offset); \
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__gfx12_set_reg((reg) + 4, __v2, base_offset); \
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ac_gfx12_set_reg((reg), __v1, base_offset); \
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ac_gfx12_set_reg((reg) + 4, __v2, base_offset); \
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BITSET_SET_RANGE_INSIDE_WORD(__tracked_regs->reg_saved_mask, (reg_enum), (reg_enum) + 1); \
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__tracked_regs->reg_value[(reg_enum)] = __v1; \
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__tracked_regs->reg_value[(reg_enum) + 1] = __v2; \
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} \
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} while (0)
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/* End the sequence and emit the packet header. */
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#define __gfx12_end_regs(header, packet) \
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do { \
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if ((header) + 1 == __cs_num) { \
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__cs_num--; /* no registers have been set, back off */ \
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} else { \
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unsigned __dw_count = __cs_num - (header) - 2; \
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__rcs->b->buf[(header)] = PKT3((packet), __dw_count, 0) | PKT3_RESET_FILTER_CAM_S(1); \
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} \
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} while (0)
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/* GFX12 generic packet building helpers for buffered registers. Don't use these directly. */
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#define __gfx12_push_reg(reg, value, base_offset) \
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do { \
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@ -267,16 +246,16 @@ radeon_check_space(struct radeon_winsys *ws, struct ac_cmdbuf *cs, unsigned need
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} while (0)
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/* GFX12 packet building helpers for PAIRS packets. */
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#define gfx12_begin_context_regs() __gfx12_begin_regs(__cs_context_reg_header)
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#define gfx12_begin_context_regs() ac_gfx12_begin_context_regs()
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#define gfx12_set_context_reg(reg, value) __gfx12_set_reg(reg, value, SI_CONTEXT_REG_OFFSET)
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#define gfx12_set_context_reg(reg, value) ac_gfx12_set_context_reg(reg, value)
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#define gfx12_opt_set_context_reg(reg, reg_enum, value) __gfx12_opt_set_reg(reg, reg_enum, value, SI_CONTEXT_REG_OFFSET)
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#define gfx12_opt_set_context_reg2(reg, reg_enum, v1, v2) \
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__gfx12_opt_set_reg2(reg, reg_enum, v1, v2, SI_CONTEXT_REG_OFFSET)
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#define gfx12_end_context_regs() __gfx12_end_regs(__cs_context_reg_header, PKT3_SET_CONTEXT_REG_PAIRS)
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#define gfx12_end_context_regs() ac_gfx12_end_context_regs()
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/* GFX12 packet building helpers for buffered registers. */
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#define gfx12_push_sh_reg(reg, value) __gfx12_push_reg(reg, value, SI_SH_REG_OFFSET)
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@ -386,18 +386,12 @@
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} while (0)
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/* GFX12 generic packet building helpers for PAIRS packets. Don't use these directly. */
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#define gfx12_begin_regs(header) unsigned header = __cs_num++
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#define gfx12_set_reg(reg, value, base_offset) do { \
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radeon_emit(((reg) - (base_offset)) >> 2); \
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radeon_emit(value); \
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} while (0)
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#define gfx12_opt_set_reg(reg, reg_enum, value, base_offset) do { \
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unsigned __value = value; \
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if (!BITSET_TEST(sctx->tracked_regs.reg_saved_mask, (reg_enum)) || \
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sctx->tracked_regs.reg_value[reg_enum] != __value) { \
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gfx12_set_reg(reg, __value, base_offset); \
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ac_gfx12_set_reg(reg, __value, base_offset); \
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BITSET_SET(sctx->tracked_regs.reg_saved_mask, (reg_enum)); \
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sctx->tracked_regs.reg_value[reg_enum] = __value; \
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} \
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@ -413,10 +407,10 @@
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sctx->tracked_regs.reg_value[(reg_enum) + 1] != __v2 || \
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sctx->tracked_regs.reg_value[(reg_enum) + 2] != __v3 || \
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sctx->tracked_regs.reg_value[(reg_enum) + 3] != __v4) { \
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gfx12_set_reg((reg), __v1, (base_offset)); \
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gfx12_set_reg((reg) + 4, __v2, (base_offset)); \
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gfx12_set_reg((reg) + 8, __v3, (base_offset)); \
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gfx12_set_reg((reg) + 12, __v4, (base_offset)); \
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ac_gfx12_set_reg((reg), __v1, (base_offset)); \
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ac_gfx12_set_reg((reg) + 4, __v2, (base_offset)); \
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ac_gfx12_set_reg((reg) + 8, __v3, (base_offset)); \
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ac_gfx12_set_reg((reg) + 12, __v4, (base_offset)); \
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BITSET_SET_RANGE_INSIDE_WORD(sctx->tracked_regs.reg_saved_mask, \
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(reg_enum), (reg_enum) + 3); \
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sctx->tracked_regs.reg_value[(reg_enum)] = __v1; \
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@ -426,15 +420,6 @@
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} \
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} while (0)
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#define gfx12_end_regs(header, packet) do { \
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if ((header) + 1 == __cs_num) { \
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__cs_num--; /* no registers have been set, back off */ \
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} else { \
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unsigned __dw_count = __cs_num - (header) - 2; \
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__cs_buf[(header)] = PKT3((packet), __dw_count, 0) | PKT3_RESET_FILTER_CAM_S(1); \
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} \
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} while (0)
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/* GFX12 generic packet building helpers for buffered registers. Don't use these directly. */
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#define gfx12_push_reg(reg, value, base_offset, type) do { \
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unsigned __i = sctx->num_buffered_##type##_regs++; \
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@ -456,10 +441,10 @@
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/* GFX12 packet building helpers for PAIRS packets. */
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#define gfx12_begin_context_regs() \
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gfx12_begin_regs(__cs_context_reg_header)
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ac_gfx12_begin_context_regs()
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#define gfx12_set_context_reg(reg, value) \
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gfx12_set_reg(reg, value, SI_CONTEXT_REG_OFFSET)
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ac_gfx12_set_context_reg(reg, value)
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#define gfx12_opt_set_context_reg(reg, reg_enum, value) \
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gfx12_opt_set_reg(reg, reg_enum, value, SI_CONTEXT_REG_OFFSET)
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@ -468,7 +453,7 @@
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gfx12_opt_set_reg4(reg, reg_enum, v1, v2, v3, v4, SI_CONTEXT_REG_OFFSET)
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#define gfx12_end_context_regs() \
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gfx12_end_regs(__cs_context_reg_header, PKT3_SET_CONTEXT_REG_PAIRS)
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ac_gfx12_end_context_regs()
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/* GFX12 packet building helpers for buffered registers. */
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#define gfx12_push_gfx_sh_reg(reg, value) \
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