diff --git a/src/amd/common/ac_cmdbuf.h b/src/amd/common/ac_cmdbuf.h index 81b651db13e..b8def98df58 100644 --- a/src/amd/common/ac_cmdbuf.h +++ b/src/amd/common/ac_cmdbuf.h @@ -135,6 +135,36 @@ struct ac_cmdbuf { ac_cmdbuf_emit(0); /* unused */ \ } while (0) +/* GFX12 generic packet building helpers for PAIRS packets. Don't use these directly. */ + +/* Reserved 1 DWORD to emit the packet header when the sequence ends. */ +#define __ac_gfx12_begin_regs(header) uint32_t header = __cs_num++ + +/* Set a register unconditionally. */ +#define ac_gfx12_set_reg(reg, value, base_offset) \ + do { \ + ac_cmdbuf_emit(((reg) - (base_offset)) >> 2); \ + ac_cmdbuf_emit(value); \ + } while (0) + +/* End the sequence and emit the packet header. */ +#define __ac_gfx12_end_regs(header, packet) \ + do { \ + if ((header) + 1 == __cs_num) { \ + __cs_num--; /* no registers have been set, back off */ \ + } else { \ + unsigned __dw_count = __cs_num - (header) - 2; \ + __cs_buf[(header)] = PKT3((packet), __dw_count, 0) | PKT3_RESET_FILTER_CAM_S(1); \ + } \ + } while (0) + +/* GFX12 packet building helpers for PAIRS packets. */ +#define ac_gfx12_begin_context_regs() __ac_gfx12_begin_regs(__cs_context_reg_header) + +#define ac_gfx12_set_context_reg(reg, value) ac_gfx12_set_reg(reg, value, SI_CONTEXT_REG_OFFSET) + +#define ac_gfx12_end_context_regs() __ac_gfx12_end_regs(__cs_context_reg_header, PKT3_SET_CONTEXT_REG_PAIRS) + struct ac_preamble_state { uint64_t border_color_va; diff --git a/src/amd/vulkan/radv_cs.h b/src/amd/vulkan/radv_cs.h index 534e3f18b19..8a52f64c158 100644 --- a/src/amd/vulkan/radv_cs.h +++ b/src/amd/vulkan/radv_cs.h @@ -208,16 +208,6 @@ radeon_check_space(struct radeon_winsys *ws, struct ac_cmdbuf *cs, unsigned need /* GFX12 generic packet building helpers for PAIRS packets. Don't use these directly. */ -/* Reserved 1 DWORD to emit the packet header when the sequence ends. */ -#define __gfx12_begin_regs(header) uint32_t header = __cs_num++ - -/* Set a register unconditionally. */ -#define __gfx12_set_reg(reg, value, base_offset) \ - do { \ - radeon_emit(((reg) - (base_offset)) >> 2); \ - radeon_emit(value); \ - } while (0) - /* Set 1 context register optimally. */ #define __gfx12_opt_set_reg(reg, reg_enum, value, base_offset) \ do { \ @@ -225,7 +215,7 @@ radeon_check_space(struct radeon_winsys *ws, struct ac_cmdbuf *cs, unsigned need const uint32_t __value = (value); \ if (!BITSET_TEST(__tracked_regs->reg_saved_mask, (reg_enum)) || \ __tracked_regs->reg_value[(reg_enum)] != __value) { \ - __gfx12_set_reg((reg), __value, base_offset); \ + ac_gfx12_set_reg((reg), __value, base_offset); \ BITSET_SET(__tracked_regs->reg_saved_mask, (reg_enum)); \ __tracked_regs->reg_value[(reg_enum)] = __value; \ } \ @@ -238,25 +228,14 @@ radeon_check_space(struct radeon_winsys *ws, struct ac_cmdbuf *cs, unsigned need const uint32_t __v1 = (v1), __v2 = (v2); \ if (!BITSET_TEST_RANGE_INSIDE_WORD(__tracked_regs->reg_saved_mask, (reg_enum), (reg_enum) + 1, 0x3) || \ __tracked_regs->reg_value[(reg_enum)] != __v1 || __tracked_regs->reg_value[(reg_enum) + 1] != __v2) { \ - __gfx12_set_reg((reg), __v1, base_offset); \ - __gfx12_set_reg((reg) + 4, __v2, base_offset); \ + ac_gfx12_set_reg((reg), __v1, base_offset); \ + ac_gfx12_set_reg((reg) + 4, __v2, base_offset); \ BITSET_SET_RANGE_INSIDE_WORD(__tracked_regs->reg_saved_mask, (reg_enum), (reg_enum) + 1); \ __tracked_regs->reg_value[(reg_enum)] = __v1; \ __tracked_regs->reg_value[(reg_enum) + 1] = __v2; \ } \ } while (0) -/* End the sequence and emit the packet header. */ -#define __gfx12_end_regs(header, packet) \ - do { \ - if ((header) + 1 == __cs_num) { \ - __cs_num--; /* no registers have been set, back off */ \ - } else { \ - unsigned __dw_count = __cs_num - (header) - 2; \ - __rcs->b->buf[(header)] = PKT3((packet), __dw_count, 0) | PKT3_RESET_FILTER_CAM_S(1); \ - } \ - } while (0) - /* GFX12 generic packet building helpers for buffered registers. Don't use these directly. */ #define __gfx12_push_reg(reg, value, base_offset) \ do { \ @@ -267,16 +246,16 @@ radeon_check_space(struct radeon_winsys *ws, struct ac_cmdbuf *cs, unsigned need } while (0) /* GFX12 packet building helpers for PAIRS packets. */ -#define gfx12_begin_context_regs() __gfx12_begin_regs(__cs_context_reg_header) +#define gfx12_begin_context_regs() ac_gfx12_begin_context_regs() -#define gfx12_set_context_reg(reg, value) __gfx12_set_reg(reg, value, SI_CONTEXT_REG_OFFSET) +#define gfx12_set_context_reg(reg, value) ac_gfx12_set_context_reg(reg, value) #define gfx12_opt_set_context_reg(reg, reg_enum, value) __gfx12_opt_set_reg(reg, reg_enum, value, SI_CONTEXT_REG_OFFSET) #define gfx12_opt_set_context_reg2(reg, reg_enum, v1, v2) \ __gfx12_opt_set_reg2(reg, reg_enum, v1, v2, SI_CONTEXT_REG_OFFSET) -#define gfx12_end_context_regs() __gfx12_end_regs(__cs_context_reg_header, PKT3_SET_CONTEXT_REG_PAIRS) +#define gfx12_end_context_regs() ac_gfx12_end_context_regs() /* GFX12 packet building helpers for buffered registers. */ #define gfx12_push_sh_reg(reg, value) __gfx12_push_reg(reg, value, SI_SH_REG_OFFSET) diff --git a/src/gallium/drivers/radeonsi/si_build_pm4.h b/src/gallium/drivers/radeonsi/si_build_pm4.h index 6abb9f228f0..fca308809c9 100644 --- a/src/gallium/drivers/radeonsi/si_build_pm4.h +++ b/src/gallium/drivers/radeonsi/si_build_pm4.h @@ -386,18 +386,12 @@ } while (0) /* GFX12 generic packet building helpers for PAIRS packets. Don't use these directly. */ -#define gfx12_begin_regs(header) unsigned header = __cs_num++ - -#define gfx12_set_reg(reg, value, base_offset) do { \ - radeon_emit(((reg) - (base_offset)) >> 2); \ - radeon_emit(value); \ -} while (0) #define gfx12_opt_set_reg(reg, reg_enum, value, base_offset) do { \ unsigned __value = value; \ if (!BITSET_TEST(sctx->tracked_regs.reg_saved_mask, (reg_enum)) || \ sctx->tracked_regs.reg_value[reg_enum] != __value) { \ - gfx12_set_reg(reg, __value, base_offset); \ + ac_gfx12_set_reg(reg, __value, base_offset); \ BITSET_SET(sctx->tracked_regs.reg_saved_mask, (reg_enum)); \ sctx->tracked_regs.reg_value[reg_enum] = __value; \ } \ @@ -413,10 +407,10 @@ sctx->tracked_regs.reg_value[(reg_enum) + 1] != __v2 || \ sctx->tracked_regs.reg_value[(reg_enum) + 2] != __v3 || \ sctx->tracked_regs.reg_value[(reg_enum) + 3] != __v4) { \ - gfx12_set_reg((reg), __v1, (base_offset)); \ - gfx12_set_reg((reg) + 4, __v2, (base_offset)); \ - gfx12_set_reg((reg) + 8, __v3, (base_offset)); \ - gfx12_set_reg((reg) + 12, __v4, (base_offset)); \ + ac_gfx12_set_reg((reg), __v1, (base_offset)); \ + ac_gfx12_set_reg((reg) + 4, __v2, (base_offset)); \ + ac_gfx12_set_reg((reg) + 8, __v3, (base_offset)); \ + ac_gfx12_set_reg((reg) + 12, __v4, (base_offset)); \ BITSET_SET_RANGE_INSIDE_WORD(sctx->tracked_regs.reg_saved_mask, \ (reg_enum), (reg_enum) + 3); \ sctx->tracked_regs.reg_value[(reg_enum)] = __v1; \ @@ -426,15 +420,6 @@ } \ } while (0) -#define gfx12_end_regs(header, packet) do { \ - if ((header) + 1 == __cs_num) { \ - __cs_num--; /* no registers have been set, back off */ \ - } else { \ - unsigned __dw_count = __cs_num - (header) - 2; \ - __cs_buf[(header)] = PKT3((packet), __dw_count, 0) | PKT3_RESET_FILTER_CAM_S(1); \ - } \ -} while (0) - /* GFX12 generic packet building helpers for buffered registers. Don't use these directly. */ #define gfx12_push_reg(reg, value, base_offset, type) do { \ unsigned __i = sctx->num_buffered_##type##_regs++; \ @@ -456,10 +441,10 @@ /* GFX12 packet building helpers for PAIRS packets. */ #define gfx12_begin_context_regs() \ - gfx12_begin_regs(__cs_context_reg_header) + ac_gfx12_begin_context_regs() #define gfx12_set_context_reg(reg, value) \ - gfx12_set_reg(reg, value, SI_CONTEXT_REG_OFFSET) + ac_gfx12_set_context_reg(reg, value) #define gfx12_opt_set_context_reg(reg, reg_enum, value) \ gfx12_opt_set_reg(reg, reg_enum, value, SI_CONTEXT_REG_OFFSET) @@ -468,7 +453,7 @@ gfx12_opt_set_reg4(reg, reg_enum, v1, v2, v3, v4, SI_CONTEXT_REG_OFFSET) #define gfx12_end_context_regs() \ - gfx12_end_regs(__cs_context_reg_header, PKT3_SET_CONTEXT_REG_PAIRS) + ac_gfx12_end_context_regs() /* GFX12 packet building helpers for buffered registers. */ #define gfx12_push_gfx_sh_reg(reg, value) \