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i965: Pass pointer to miptree as function parameter in intel_horizontal_texture_alignment_unit

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This will be used by next patch in the series.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Neil Roberts <neil@linux.intel.com>
This commit is contained in:
Anuj Phogat 2015-02-20 12:26:36 -08:00
parent 94d88cb468
commit 84199fa647
1 changed files with 6 additions and 6 deletions
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12
src/mesa/drivers/dri/i965/brw_tex_layout.c
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@ -41,7 +41,7 @@
static unsigned int
intel_horizontal_texture_alignment_unit(struct brw_context *brw,
mesa_format format)
struct intel_mipmap_tree *mt)
{
/**
* From the "Alignment Unit Size" section of various specs, namely:
@ -67,19 +67,19 @@ intel_horizontal_texture_alignment_unit(struct brw_context *brw,
* On IVB+, non-special cases can be overridden by setting the SURFACE_STATE
* "Surface Horizontal Alignment" field to HALIGN_4 or HALIGN_8.
*/
if (_mesa_is_format_compressed(format)) {
if (_mesa_is_format_compressed(mt->format)) {
/* The hardware alignment requirements for compressed textures
* happen to match the block boundaries.
*/
unsigned int i, j;
_mesa_get_format_block_size(format, &i, &j);
_mesa_get_format_block_size(mt->format, &i, &j);
return i;
}
if (format == MESA_FORMAT_S_UINT8)
if (mt->format == MESA_FORMAT_S_UINT8)
return 8;
if (brw->gen >= 7 && format == MESA_FORMAT_Z_UNORM16)
if (brw->gen >= 7 && mt->format == MESA_FORMAT_Z_UNORM16)
return 8;
return 4;
@ -350,7 +350,7 @@ brw_miptree_layout(struct brw_context *brw, struct intel_mipmap_tree *mt)
mt->align_h = 32;
}
} else {
mt->align_w = intel_horizontal_texture_alignment_unit(brw, mt->format);
mt->align_w = intel_horizontal_texture_alignment_unit(brw, mt);
mt->align_h =
intel_vertical_texture_alignment_unit(brw, mt->format, multisampled);
}