fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-09 06:48:06 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

intel/compiler: Adjust trace ray control field on Xe2

Browse source 
Bspec 64643: Structure_TraceRayPayload::Trace Ray Control

Bit field moved from 9-8 to 10-8 on Xe2.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30600>
This commit is contained in:
Sagar Ghuge 2024-08-09 23:06:30 -07:00 • committed by Marge Bot
parent c3c62e493f
commit 83c2524124
1 changed files with 2 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
src/intel/compiler/brw_lower_logical_sends.cpp
View file

@ -2675,7 +2675,8 @@ lower_trace_ray_logical_send(const fs_builder &bld, fs_inst *inst)
brw_reg payload = bld.vgrf(BRW_TYPE_UD);
if (bvh_level.file == BRW_IMMEDIATE_VALUE &&
trace_ray_control.file == BRW_IMMEDIATE_VALUE) {
bld.MOV(payload, brw_imm_ud(SET_BITS(trace_ray_control.ud, 9, 8) |
uint32_t high = devinfo->ver >= 20 ? 10 : 9;
bld.MOV(payload, brw_imm_ud(SET_BITS(trace_ray_control.ud, high, 8) |
(bvh_level.ud & 0x7)));
} else {
bld.SHL(payload, trace_ray_control, brw_imm_ud(8));