From 83c25241246f67617e3ec27451546e117261d1ae Mon Sep 17 00:00:00 2001
From: Sagar Ghuge <sagar.ghuge@intel.com>
Date: Fri, 9 Aug 2024 23:06:30 -0700
Subject: [PATCH] intel/compiler: Adjust trace ray control field on Xe2

Bspec 64643: Structure_TraceRayPayload::Trace Ray Control

Bit field moved from 9-8 to 10-8 on Xe2.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30600>
---
 src/intel/compiler/brw_lower_logical_sends.cpp | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/intel/compiler/brw_lower_logical_sends.cpp b/src/intel/compiler/brw_lower_logical_sends.cpp
index 50477ad9db6..5819c4cf282 100644
--- a/src/intel/compiler/brw_lower_logical_sends.cpp
+++ b/src/intel/compiler/brw_lower_logical_sends.cpp
@@ -2675,7 +2675,8 @@ lower_trace_ray_logical_send(const fs_builder &bld, fs_inst *inst)
    brw_reg payload = bld.vgrf(BRW_TYPE_UD);
    if (bvh_level.file == BRW_IMMEDIATE_VALUE &&
        trace_ray_control.file == BRW_IMMEDIATE_VALUE) {
-      bld.MOV(payload, brw_imm_ud(SET_BITS(trace_ray_control.ud, 9, 8) |
+      uint32_t high = devinfo->ver >= 20 ? 10 : 9;
+      bld.MOV(payload, brw_imm_ud(SET_BITS(trace_ray_control.ud, high, 8) |
                                   (bvh_level.ud & 0x7)));
    } else {
       bld.SHL(payload, trace_ray_control, brw_imm_ud(8));