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freedreno/a6xx+ir3: stop generating pointless binning shaders

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Currently we always do sysmem if there is tess.  And for GS, the binning
pass VS ends up identical to the draw pass VS, so no point in compiling
it twice.  (For GS what we should do someday is generate a binning pass
GS, and possibly if we can do cross-stage linking opts, an optimized
binning pass VS, but the required outputs would somehow have to end up
in the shader variant key.)

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5372>
This commit is contained in:
Rob Clark 2020-06-20 12:39:14 -07:00
parent fdbe1ffaf7
commit 83b97bf161
4 changed files with 21 additions and 13 deletions
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11
src/freedreno/ir3/ir3_shader.h
View file

@ -643,6 +643,17 @@ ir3_shader_stage(struct ir3_shader_variant *v)
}
}
/* Currently we do not do binning for tess. And for GS there is no
* cross-stage VS+GS optimization, so the full VS+GS is used in
* the binning pass.
*/
static inline bool
ir3_has_binning_vs(const struct ir3_shader_key *key)
{
if (key->tessellation || key->has_gs)
return false;
return true;
}
/**
* Represents a shader at the API level, before state-specific variants are

3
src/freedreno/vulkan/tu_pipeline.c
View file

@ -2001,7 +2001,8 @@ tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder,
const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
struct ir3_shader_variant *variant;
if (vs->ir3_shader->stream_output.num_outputs) {
if (vs->ir3_shader->stream_output.num_outputs ||
!ir3_has_binning_vs(&key)) {
variant = builder->variants[MESA_SHADER_VERTEX];
} else {
bool created;

5
src/gallium/drivers/freedreno/a6xx/fd6_program.c
View file

@ -228,10 +228,7 @@ setup_config_stateobj(struct fd_ringbuffer *ring, struct fd6_program_state *stat
OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
OUT_RING(ring, 0xff); /* XXX */
if (state->ds)
debug_assert(state->ds->constlen >= state->bs->constlen);
else
debug_assert(state->vs->constlen >= state->bs->constlen);
debug_assert(state->vs->constlen >= state->bs->constlen);
OUT_PKT4(ring, REG_A6XX_HLSQ_VS_CNTL, 4);
OUT_RING(ring, A6XX_HLSQ_VS_CNTL_CONSTLEN(state->vs->constlen) |

15
src/gallium/drivers/freedreno/ir3/ir3_cache.c
View file

@ -132,17 +132,16 @@ ir3_cache_lookup(struct ir3_cache *cache, const struct ir3_cache_key *key,
}
}
/* For tessellation, the binning shader is derived from the DS. */
struct ir3_shader_variant *bs;
if (key->ds) {
shader_key.safe_constlen = !!(safe_constlens & (1 << MESA_SHADER_TESS_EVAL));
bs = ir3_shader_variant(key->ds, shader_key, true, debug);
} else {
if (ir3_has_binning_vs(&key->key)) {
shader_key.safe_constlen = !!(safe_constlens & (1 << MESA_SHADER_VERTEX));
bs = ir3_shader_variant(key->vs, shader_key, true, debug);
bs = ir3_shader_variant(key->vs, key->key, true, debug);
if (!bs)
return NULL;
} else {
bs = variants[MESA_SHADER_VERTEX];
}
if (!bs)
return NULL;
struct ir3_program_state *state =
cache->funcs->create_state(cache->data, bs,