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iris: migrate WA 14013910100 to use the WA framework

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Fixes: eeb3f4594d ("intel/xehp: Implement XeHP workaround Wa_14013910100.")
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24156>
This commit is contained in:
Rohan Garg 2023-07-14 12:15:33 +02:00
parent e85a18a9af
commit 83716b08cf
1 changed files with 3 additions and 2 deletions
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5
src/gallium/drivers/iris/iris_state.c
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@ -430,6 +430,7 @@ flush_before_state_base_change(struct iris_batch *batch)
static void static void
flush_after_state_base_change(struct iris_batch *batch) flush_after_state_base_change(struct iris_batch *batch)
{ {
const struct intel_device_info *devinfo = batch->screen->devinfo;
/* After re-setting the surface state base address, we have to do some /* After re-setting the surface state base address, we have to do some
* cache flusing so that the sampler engine will pick up the new * cache flusing so that the sampler engine will pick up the new
* SURFACE_STATE objects and binding tables. From the Broadwell PRM, * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
@ -467,7 +468,7 @@ flush_after_state_base_change(struct iris_batch *batch)
* units cache the binding table in the texture cache. However, we have * units cache the binding table in the texture cache. However, we have
* yet to be able to actually confirm this. * yet to be able to actually confirm this.
* *
* Wa_14013910100: * Wa_16013000631:
* *
* "DG2 128/256/512-A/B: S/W must program STATE_BASE_ADDRESS command twice * "DG2 128/256/512-A/B: S/W must program STATE_BASE_ADDRESS command twice
* or program pipe control with Instruction cache invalidate post * or program pipe control with Instruction cache invalidate post
@ -478,7 +479,7 @@ flush_after_state_base_change(struct iris_batch *batch)
PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
PIPE_CONTROL_CONST_CACHE_INVALIDATE | PIPE_CONTROL_CONST_CACHE_INVALIDATE |
PIPE_CONTROL_STATE_CACHE_INVALIDATE | PIPE_CONTROL_STATE_CACHE_INVALIDATE |
(GFX_VERx10 != 125 ? 0 : (intel_needs_workaround(devinfo, 16013000631) ? 0 :
PIPE_CONTROL_INSTRUCTION_INVALIDATE)); PIPE_CONTROL_INSTRUCTION_INVALIDATE));
} }