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amd: drop support for LLVM 15, 16, 17

Browse source 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33211>
This commit is contained in:
Marek Olšák 2025-01-24 10:40:18 -05:00 • committed by Marge Bot
parent 5ca23eff0b
commit 82047fa82f
12 changed files with 11 additions and 76 deletions
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4
meson.build
View file

@ -1764,7 +1764,9 @@ amd_with_llvm = get_option('amd-use-llvm')
llvm_has_mcjit = host_machine.cpu_family() in ['aarch64', 'arm', 'ppc', 'ppc64', 's390x', 'x86', 'x86_64']
llvm_with_orcjit = get_option('llvm-orcjit') or not llvm_has_mcjit
if with_amd_vk or with_gallium_radeonsi or with_clc or llvm_with_orcjit
if with_amd_vk or with_gallium_radeonsi
_llvm_version = '>= 18.0.0'
elif with_clc or llvm_with_orcjit
_llvm_version = '>= 15.0.0'
elif with_gallium_clover
_llvm_version = '>= 11.0.0'

10
src/amd/common/amd_family.c
View file

@ -9,10 +9,6 @@
#include "util/macros.h"
#include "ac_gpu_info.h"
#if AMD_LLVM_AVAILABLE
#include <llvm/Config/llvm-config.h>
#endif
const char *ac_get_family_name(enum radeon_family family)
{
switch (family) {
@ -146,11 +142,7 @@ const char *ac_get_llvm_processor_name(enum radeon_family family)
case CHIP_MI200:
return "gfx90a";
case CHIP_GFX940:
return
#if AMD_LLVM_AVAILABLE
LLVM_VERSION_MAJOR >= 17 ? "gfx942" :
#endif
"gfx940";
return "gfx942";
case CHIP_NAVI10:
return "gfx1010";
case CHIP_NAVI12:

11
src/amd/llvm/ac_llvm_build.c
View file

@ -2605,9 +2605,8 @@ LLVMValueRef ac_build_writelane(struct ac_llvm_context *ctx, LLVMValueRef src, L
(LLVMValueRef[]){value, lane, src}, 3, 0);
}
LLVMValueRef ac_build_mbcnt_add(struct ac_llvm_context *ctx, LLVMValueRef mask, LLVMValueRef add_src)
LLVMValueRef ac_build_mbcnt_add(struct ac_llvm_context *ctx, LLVMValueRef mask, LLVMValueRef add)
{
LLVMValueRef add = LLVM_VERSION_MAJOR >= 16 ? add_src : ctx->i32_0;
LLVMValueRef val;
if (ctx->wave_size == 32) {
@ -2629,14 +2628,6 @@ LLVMValueRef ac_build_mbcnt_add(struct ac_llvm_context *ctx, LLVMValueRef mask,
if (add == ctx->i32_0)
ac_set_range_metadata(ctx, val, 0, ctx->wave_size);
if (LLVM_VERSION_MAJOR < 16) {
/* Bug workaround. LLVM always believes the upper bound of mbcnt to be the wave size,
* regardless of ac_set_range_metadata. Use an extra add instruction to work around it.
*/
ac_set_range_metadata(ctx, val, 0, ctx->wave_size);
val = LLVMBuildAdd(ctx->builder, val, add_src, "");
}
return val;
}

2
src/amd/llvm/ac_llvm_build.h
View file

@ -435,7 +435,7 @@ LLVMValueRef ac_build_readlane(struct ac_llvm_context *ctx, LLVMValueRef src, LL
LLVMValueRef ac_build_writelane(struct ac_llvm_context *ctx, LLVMValueRef src, LLVMValueRef value,
LLVMValueRef lane);
LLVMValueRef ac_build_mbcnt_add(struct ac_llvm_context *ctx, LLVMValueRef mask, LLVMValueRef add_src);
LLVMValueRef ac_build_mbcnt_add(struct ac_llvm_context *ctx, LLVMValueRef mask, LLVMValueRef add);
LLVMValueRef ac_build_mbcnt(struct ac_llvm_context *ctx, LLVMValueRef mask);
LLVMValueRef ac_build_wqm(struct ac_llvm_context *ctx, LLVMValueRef src);

9
src/amd/llvm/ac_llvm_helper.cpp
View file

@ -270,12 +270,7 @@ struct ac_midend_optimizer
/* The following set of passes run on an individual function/loop first
* before proceeding to the next.
*/
#if LLVM_VERSION_MAJOR >= 16
function_pm.addPass(SROAPass(SROAOptions::ModifyCFG));
#else
// Old version of the code
function_pm.addPass(SROAPass());
#endif
loop_pm.addPass(LICMPass(LICMOptions()));
function_pm.addPass(createFunctionToLoopPassAdaptor(std::move(loop_pm), true));
@ -318,11 +313,7 @@ struct ac_backend_optimizer
{
/* add backend passes */
if (arg_target_machine->addPassesToEmitFile(backend_pass_manager, ostream, nullptr,
#if LLVM_VERSION_MAJOR >= 18
CodeGenFileType::ObjectFile)) {
#else
CGFT_ObjectFile)) {
#endif
fprintf(stderr, "amd: TargetMachine can't emit a file of this type!\n");
}
}

15
src/amd/llvm/ac_nir_to_llvm.c
View file

@ -846,20 +846,11 @@ static bool visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
case nir_op_ldexp:
src[0] = ac_to_float(&ctx->ac, src[0]);
if (ac_get_elem_bits(&ctx->ac, def_type) == 32)
result = ac_build_intrinsic(&ctx->ac,
LLVM_VERSION_MAJOR >= 18 ? "llvm.ldexp.f32.i32"
: "llvm.amdgcn.ldexp.f32",
ctx->ac.f32, src, 2, 0);
result = ac_build_intrinsic(&ctx->ac, "llvm.ldexp.f32.i32", ctx->ac.f32, src, 2, 0);
else if (ac_get_elem_bits(&ctx->ac, def_type) == 16)
result = ac_build_intrinsic(&ctx->ac,
LLVM_VERSION_MAJOR >= 18 ? "llvm.ldexp.f16.i32"
: "llvm.amdgcn.ldexp.f16",
ctx->ac.f16, src, 2, 0);
result = ac_build_intrinsic(&ctx->ac, "llvm.ldexp.f16.i32", ctx->ac.f16, src, 2, 0);
else
result = ac_build_intrinsic(&ctx->ac,
LLVM_VERSION_MAJOR >= 18 ? "llvm.ldexp.f64.i32"
: "llvm.amdgcn.ldexp.f64",
ctx->ac.f64, src, 2, 0);
result = ac_build_intrinsic(&ctx->ac, "llvm.ldexp.f64.i32", ctx->ac.f64, src, 2, 0);
break;
case nir_op_bfm:
result = emit_bfm(&ctx->ac, src[0], src[1]);

4
src/amd/vulkan/nir/radv_nir_rt_common.c
View file

@ -8,10 +8,6 @@
#include "bvh/bvh.h"
#include "radv_debug.h"
#if AMD_LLVM_AVAILABLE
#include <llvm/Config/llvm-config.h>
#endif
static nir_def *build_node_to_addr(struct radv_device *device, nir_builder *b, nir_def *node, bool skip_type_and);
static void

4
src/amd/vulkan/radv_device.c
View file

@ -68,10 +68,6 @@ typedef void *drmDevicePtr;
#include "vk_sync.h"
#include "vk_sync_dummy.h"
#if AMD_LLVM_AVAILABLE
#include "ac_llvm_util.h"
#endif
#include "ac_descriptors.h"
#include "ac_formats.h"

11
src/amd/vulkan/radv_pipeline.c
View file

@ -37,9 +37,6 @@
#include "vk_format.h"
#include "vk_nir_convert_ycbcr.h"
#include "vk_ycbcr_conversion.h"
#if AMD_LLVM_AVAILABLE
#include "ac_llvm_util.h"
#endif
bool
radv_shader_need_indirect_descriptor_sets(const struct radv_shader *shader)
@ -306,17 +303,13 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_graphics_stat
/* LLVM could support more of these in theory. */
bool use_llvm = radv_use_llvm_for_stage(pdev, stage->stage);
bool has_inverse_ballot = true;
#if AMD_LLVM_AVAILABLE
has_inverse_ballot = !use_llvm || LLVM_VERSION_MAJOR >= 17;
#endif
radv_nir_opt_tid_function_options tid_options = {
.use_masked_swizzle_amd = true,
.use_dpp16_shift_amd = !use_llvm && gfx_level >= GFX8,
.use_clustered_rotate = !use_llvm,
.hw_subgroup_size = stage->info.wave_size,
.hw_ballot_bit_size = has_inverse_ballot ? stage->info.wave_size : 0,
.hw_ballot_num_comp = has_inverse_ballot ? 1 : 0,
.hw_ballot_bit_size = stage->info.wave_size,
.hw_ballot_num_comp = 1,
};
NIR_PASS(_, stage->nir, radv_nir_opt_tid_function, &tid_options);

5
src/amd/vulkan/radv_shader.c
View file

@ -541,11 +541,7 @@ radv_shader_spirv_to_nir(struct radv_device *device, const struct radv_shader_st
NIR_PASS(_, nir, nir_remove_dead_variables, nir_var_function_temp, NULL);
bool gfx7minus = pdev->info.gfx_level <= GFX7;
bool has_inverse_ballot = true;
bool use_llvm = radv_use_llvm_for_stage(pdev, nir->info.stage);
#if AMD_LLVM_AVAILABLE
has_inverse_ballot = !use_llvm || LLVM_VERSION_MAJOR >= 17;
#endif
NIR_PASS(_, nir, nir_lower_subgroups,
&(struct nir_lower_subgroups_options){
@ -563,7 +559,6 @@ radv_shader_spirv_to_nir(struct radv_device *device, const struct radv_shader_st
.lower_quad_broadcast_dynamic_to_const = gfx7minus,
.lower_shuffle_to_swizzle_amd = 1,
.lower_ballot_bit_count_to_mbcnt_amd = 1,
.lower_inverse_ballot = !has_inverse_ballot,
.lower_boolean_reduce = !use_llvm,
.lower_boolean_shuffle = true,
});

8
src/gallium/drivers/radeonsi/si_shader.c
View file

@ -20,14 +20,7 @@
#include "util/ralloc.h"
#include "util/u_upload_mgr.h"
#if LLVM_AVAILABLE
#include <llvm/Config/llvm-config.h> /* for LLVM_VERSION_MAJOR */
#else
#define LLVM_VERSION_MAJOR 0
#endif
static const char scratch_rsrc_dword0_symbol[] = "SCRATCH_RSRC_DWORD0";
static const char scratch_rsrc_dword1_symbol[] = "SCRATCH_RSRC_DWORD1";
static void si_dump_shader_key(const struct si_shader *shader, FILE *f);
@ -2507,7 +2500,6 @@ static void run_late_optimization_and_lowering_passes(struct si_nir_shader_ctx *
.lower_quad_broadcast_dynamic_to_const = sel->screen->info.gfx_level <= GFX7,
.lower_shuffle_to_swizzle_amd = true,
.lower_ballot_bit_count_to_mbcnt_amd = true,
.lower_inverse_ballot = !nir->info.use_aco_amd && LLVM_VERSION_MAJOR < 17,
.lower_boolean_reduce = nir->info.use_aco_amd,
.lower_boolean_shuffle = true,
});

4
src/gallium/drivers/radeonsi/si_state_shaders.cpp
View file

@ -4,10 +4,6 @@
* SPDX-License-Identifier: MIT
*/
#if AMD_LLVM_AVAILABLE
#include "ac_llvm_util.h"
#endif
#include "ac_nir.h"
#include "ac_shader_util.h"
#include "compiler/nir/nir_serialize.h"