diff --git a/meson.build b/meson.build index 181ebee9c9d..e3096a84708 100644 --- a/meson.build +++ b/meson.build @@ -1764,7 +1764,9 @@ amd_with_llvm = get_option('amd-use-llvm') llvm_has_mcjit = host_machine.cpu_family() in ['aarch64', 'arm', 'ppc', 'ppc64', 's390x', 'x86', 'x86_64'] llvm_with_orcjit = get_option('llvm-orcjit') or not llvm_has_mcjit -if with_amd_vk or with_gallium_radeonsi or with_clc or llvm_with_orcjit +if with_amd_vk or with_gallium_radeonsi + _llvm_version = '>= 18.0.0' +elif with_clc or llvm_with_orcjit _llvm_version = '>= 15.0.0' elif with_gallium_clover _llvm_version = '>= 11.0.0' diff --git a/src/amd/common/amd_family.c b/src/amd/common/amd_family.c index 09e84127439..dcc96df76d7 100644 --- a/src/amd/common/amd_family.c +++ b/src/amd/common/amd_family.c @@ -9,10 +9,6 @@ #include "util/macros.h" #include "ac_gpu_info.h" -#if AMD_LLVM_AVAILABLE -#include -#endif - const char *ac_get_family_name(enum radeon_family family) { switch (family) { @@ -146,11 +142,7 @@ const char *ac_get_llvm_processor_name(enum radeon_family family) case CHIP_MI200: return "gfx90a"; case CHIP_GFX940: - return -#if AMD_LLVM_AVAILABLE - LLVM_VERSION_MAJOR >= 17 ? "gfx942" : -#endif - "gfx940"; + return "gfx942"; case CHIP_NAVI10: return "gfx1010"; case CHIP_NAVI12: diff --git a/src/amd/llvm/ac_llvm_build.c b/src/amd/llvm/ac_llvm_build.c index 514dc885833..427189e9b80 100644 --- a/src/amd/llvm/ac_llvm_build.c +++ b/src/amd/llvm/ac_llvm_build.c @@ -2605,9 +2605,8 @@ LLVMValueRef ac_build_writelane(struct ac_llvm_context *ctx, LLVMValueRef src, L (LLVMValueRef[]){value, lane, src}, 3, 0); } -LLVMValueRef ac_build_mbcnt_add(struct ac_llvm_context *ctx, LLVMValueRef mask, LLVMValueRef add_src) +LLVMValueRef ac_build_mbcnt_add(struct ac_llvm_context *ctx, LLVMValueRef mask, LLVMValueRef add) { - LLVMValueRef add = LLVM_VERSION_MAJOR >= 16 ? add_src : ctx->i32_0; LLVMValueRef val; if (ctx->wave_size == 32) { @@ -2629,14 +2628,6 @@ LLVMValueRef ac_build_mbcnt_add(struct ac_llvm_context *ctx, LLVMValueRef mask, if (add == ctx->i32_0) ac_set_range_metadata(ctx, val, 0, ctx->wave_size); - if (LLVM_VERSION_MAJOR < 16) { - /* Bug workaround. LLVM always believes the upper bound of mbcnt to be the wave size, - * regardless of ac_set_range_metadata. Use an extra add instruction to work around it. - */ - ac_set_range_metadata(ctx, val, 0, ctx->wave_size); - val = LLVMBuildAdd(ctx->builder, val, add_src, ""); - } - return val; } diff --git a/src/amd/llvm/ac_llvm_build.h b/src/amd/llvm/ac_llvm_build.h index 4fbcbdcd86f..2e5df630049 100644 --- a/src/amd/llvm/ac_llvm_build.h +++ b/src/amd/llvm/ac_llvm_build.h @@ -435,7 +435,7 @@ LLVMValueRef ac_build_readlane(struct ac_llvm_context *ctx, LLVMValueRef src, LL LLVMValueRef ac_build_writelane(struct ac_llvm_context *ctx, LLVMValueRef src, LLVMValueRef value, LLVMValueRef lane); -LLVMValueRef ac_build_mbcnt_add(struct ac_llvm_context *ctx, LLVMValueRef mask, LLVMValueRef add_src); +LLVMValueRef ac_build_mbcnt_add(struct ac_llvm_context *ctx, LLVMValueRef mask, LLVMValueRef add); LLVMValueRef ac_build_mbcnt(struct ac_llvm_context *ctx, LLVMValueRef mask); LLVMValueRef ac_build_wqm(struct ac_llvm_context *ctx, LLVMValueRef src); diff --git a/src/amd/llvm/ac_llvm_helper.cpp b/src/amd/llvm/ac_llvm_helper.cpp index e02c9c3fd07..1b6c955caa4 100644 --- a/src/amd/llvm/ac_llvm_helper.cpp +++ b/src/amd/llvm/ac_llvm_helper.cpp @@ -270,12 +270,7 @@ struct ac_midend_optimizer /* The following set of passes run on an individual function/loop first * before proceeding to the next. */ -#if LLVM_VERSION_MAJOR >= 16 function_pm.addPass(SROAPass(SROAOptions::ModifyCFG)); -#else - // Old version of the code - function_pm.addPass(SROAPass()); -#endif loop_pm.addPass(LICMPass(LICMOptions())); function_pm.addPass(createFunctionToLoopPassAdaptor(std::move(loop_pm), true)); @@ -318,11 +313,7 @@ struct ac_backend_optimizer { /* add backend passes */ if (arg_target_machine->addPassesToEmitFile(backend_pass_manager, ostream, nullptr, -#if LLVM_VERSION_MAJOR >= 18 CodeGenFileType::ObjectFile)) { -#else - CGFT_ObjectFile)) { -#endif fprintf(stderr, "amd: TargetMachine can't emit a file of this type!\n"); } } diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c index cb48ec7a822..3beb20f6abb 100644 --- a/src/amd/llvm/ac_nir_to_llvm.c +++ b/src/amd/llvm/ac_nir_to_llvm.c @@ -846,20 +846,11 @@ static bool visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr) case nir_op_ldexp: src[0] = ac_to_float(&ctx->ac, src[0]); if (ac_get_elem_bits(&ctx->ac, def_type) == 32) - result = ac_build_intrinsic(&ctx->ac, - LLVM_VERSION_MAJOR >= 18 ? "llvm.ldexp.f32.i32" - : "llvm.amdgcn.ldexp.f32", - ctx->ac.f32, src, 2, 0); + result = ac_build_intrinsic(&ctx->ac, "llvm.ldexp.f32.i32", ctx->ac.f32, src, 2, 0); else if (ac_get_elem_bits(&ctx->ac, def_type) == 16) - result = ac_build_intrinsic(&ctx->ac, - LLVM_VERSION_MAJOR >= 18 ? "llvm.ldexp.f16.i32" - : "llvm.amdgcn.ldexp.f16", - ctx->ac.f16, src, 2, 0); + result = ac_build_intrinsic(&ctx->ac, "llvm.ldexp.f16.i32", ctx->ac.f16, src, 2, 0); else - result = ac_build_intrinsic(&ctx->ac, - LLVM_VERSION_MAJOR >= 18 ? "llvm.ldexp.f64.i32" - : "llvm.amdgcn.ldexp.f64", - ctx->ac.f64, src, 2, 0); + result = ac_build_intrinsic(&ctx->ac, "llvm.ldexp.f64.i32", ctx->ac.f64, src, 2, 0); break; case nir_op_bfm: result = emit_bfm(&ctx->ac, src[0], src[1]); diff --git a/src/amd/vulkan/nir/radv_nir_rt_common.c b/src/amd/vulkan/nir/radv_nir_rt_common.c index 4176436cf66..8a2da29933a 100644 --- a/src/amd/vulkan/nir/radv_nir_rt_common.c +++ b/src/amd/vulkan/nir/radv_nir_rt_common.c @@ -8,10 +8,6 @@ #include "bvh/bvh.h" #include "radv_debug.h" -#if AMD_LLVM_AVAILABLE -#include -#endif - static nir_def *build_node_to_addr(struct radv_device *device, nir_builder *b, nir_def *node, bool skip_type_and); static void diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 2de839e5d6d..01c7ad45caf 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -68,10 +68,6 @@ typedef void *drmDevicePtr; #include "vk_sync.h" #include "vk_sync_dummy.h" -#if AMD_LLVM_AVAILABLE -#include "ac_llvm_util.h" -#endif - #include "ac_descriptors.h" #include "ac_formats.h" diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 46ffc0ceb06..591fc48577a 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -37,9 +37,6 @@ #include "vk_format.h" #include "vk_nir_convert_ycbcr.h" #include "vk_ycbcr_conversion.h" -#if AMD_LLVM_AVAILABLE -#include "ac_llvm_util.h" -#endif bool radv_shader_need_indirect_descriptor_sets(const struct radv_shader *shader) @@ -306,17 +303,13 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_graphics_stat /* LLVM could support more of these in theory. */ bool use_llvm = radv_use_llvm_for_stage(pdev, stage->stage); - bool has_inverse_ballot = true; -#if AMD_LLVM_AVAILABLE - has_inverse_ballot = !use_llvm || LLVM_VERSION_MAJOR >= 17; -#endif radv_nir_opt_tid_function_options tid_options = { .use_masked_swizzle_amd = true, .use_dpp16_shift_amd = !use_llvm && gfx_level >= GFX8, .use_clustered_rotate = !use_llvm, .hw_subgroup_size = stage->info.wave_size, - .hw_ballot_bit_size = has_inverse_ballot ? stage->info.wave_size : 0, - .hw_ballot_num_comp = has_inverse_ballot ? 1 : 0, + .hw_ballot_bit_size = stage->info.wave_size, + .hw_ballot_num_comp = 1, }; NIR_PASS(_, stage->nir, radv_nir_opt_tid_function, &tid_options); diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index bf0edba5373..adc58db5fd8 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -541,11 +541,7 @@ radv_shader_spirv_to_nir(struct radv_device *device, const struct radv_shader_st NIR_PASS(_, nir, nir_remove_dead_variables, nir_var_function_temp, NULL); bool gfx7minus = pdev->info.gfx_level <= GFX7; - bool has_inverse_ballot = true; bool use_llvm = radv_use_llvm_for_stage(pdev, nir->info.stage); -#if AMD_LLVM_AVAILABLE - has_inverse_ballot = !use_llvm || LLVM_VERSION_MAJOR >= 17; -#endif NIR_PASS(_, nir, nir_lower_subgroups, &(struct nir_lower_subgroups_options){ @@ -563,7 +559,6 @@ radv_shader_spirv_to_nir(struct radv_device *device, const struct radv_shader_st .lower_quad_broadcast_dynamic_to_const = gfx7minus, .lower_shuffle_to_swizzle_amd = 1, .lower_ballot_bit_count_to_mbcnt_amd = 1, - .lower_inverse_ballot = !has_inverse_ballot, .lower_boolean_reduce = !use_llvm, .lower_boolean_shuffle = true, }); diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index 88ba3a1f499..7a9274ff3b0 100644 --- a/src/gallium/drivers/radeonsi/si_shader.c +++ b/src/gallium/drivers/radeonsi/si_shader.c @@ -20,14 +20,7 @@ #include "util/ralloc.h" #include "util/u_upload_mgr.h" -#if LLVM_AVAILABLE -#include /* for LLVM_VERSION_MAJOR */ -#else -#define LLVM_VERSION_MAJOR 0 -#endif - static const char scratch_rsrc_dword0_symbol[] = "SCRATCH_RSRC_DWORD0"; - static const char scratch_rsrc_dword1_symbol[] = "SCRATCH_RSRC_DWORD1"; static void si_dump_shader_key(const struct si_shader *shader, FILE *f); @@ -2507,7 +2500,6 @@ static void run_late_optimization_and_lowering_passes(struct si_nir_shader_ctx * .lower_quad_broadcast_dynamic_to_const = sel->screen->info.gfx_level <= GFX7, .lower_shuffle_to_swizzle_amd = true, .lower_ballot_bit_count_to_mbcnt_amd = true, - .lower_inverse_ballot = !nir->info.use_aco_amd && LLVM_VERSION_MAJOR < 17, .lower_boolean_reduce = nir->info.use_aco_amd, .lower_boolean_shuffle = true, }); diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.cpp b/src/gallium/drivers/radeonsi/si_state_shaders.cpp index 4b96ce375c6..88c8e5f3062 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.cpp +++ b/src/gallium/drivers/radeonsi/si_state_shaders.cpp @@ -4,10 +4,6 @@ * SPDX-License-Identifier: MIT */ -#if AMD_LLVM_AVAILABLE -#include "ac_llvm_util.h" -#endif - #include "ac_nir.h" #include "ac_shader_util.h" #include "compiler/nir/nir_serialize.h"