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intel/brw/xe3+: Mask subgroup shuffle index to be within valid range to avoid VRT hangs.

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Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32664>
This commit is contained in:
Francisco Jerez 2025-01-23 20:53:16 -08:00 • committed by Marge Bot
parent d2af77aa6b
commit 8102500b95
1 changed files with 11 additions and 1 deletions
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12
src/intel/compiler/brw_fs_nir.cpp
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@ -6497,7 +6497,17 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb,
case nir_intrinsic_shuffle: {
const brw_reg value = get_nir_src(ntb, instr->src[0]);
const brw_reg index = get_nir_src(ntb, instr->src[1]);
brw_reg index = get_nir_src(ntb, instr->src[1]);
if (devinfo->ver >= 30) {
/* Mask index to constrain it to be within the valid range in
* order to avoid potentially reading past the end of the GRF
* file, which can lead to hangs on Xe3+ with VRT enabled.
*/
const brw_reg tmp = bld.vgrf(BRW_TYPE_UD);
bld.AND(tmp, index, brw_imm_ud(s.dispatch_width - 1));
index = tmp;
}
bld.emit(SHADER_OPCODE_SHUFFLE, retype(dest, value.type), value, index);
break;