diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index 7e39e22eaef..121e0f777b8 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -6497,7 +6497,17 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb,
 
    case nir_intrinsic_shuffle: {
       const brw_reg value = get_nir_src(ntb, instr->src[0]);
-      const brw_reg index = get_nir_src(ntb, instr->src[1]);
+      brw_reg index = get_nir_src(ntb, instr->src[1]);
+
+      if (devinfo->ver >= 30) {
+         /* Mask index to constrain it to be within the valid range in
+          * order to avoid potentially reading past the end of the GRF
+          * file, which can lead to hangs on Xe3+ with VRT enabled.
+          */
+         const brw_reg tmp = bld.vgrf(BRW_TYPE_UD);
+         bld.AND(tmp, index, brw_imm_ud(s.dispatch_width - 1));
+         index = tmp;
+      }
 
       bld.emit(SHADER_OPCODE_SHUFFLE, retype(dest, value.type), value, index);
       break;