From 80fb55571860ae3cc092f8a2646425e5f20bb5bf Mon Sep 17 00:00:00 2001 From: Caio Oliveira Date: Mon, 2 Jun 2025 15:59:34 -0700 Subject: [PATCH] brw: Fix MAD instruction usage in spilling logic The intention here is to build a SIMD8 value, that will be expanded as needed -- just like the SHL/ADD case, but with a single instruction. Found when the was triggering invalid MAD with SIMD32 (that gets compressed) *and* with overlapping destination and source *and* which would cause conflict when divided into two SIMD16. Fixes: 338273dedde ("brw/reg_allocate: Optimize spill offset calculation using integer MAD") Reviewed-by: Ian Romanick Part-of: --- src/intel/compiler/brw_reg_allocate.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/intel/compiler/brw_reg_allocate.cpp b/src/intel/compiler/brw_reg_allocate.cpp index cc1cdd4f401..81a51369b96 100644 --- a/src/intel/compiler/brw_reg_allocate.cpp +++ b/src/intel/compiler/brw_reg_allocate.cpp @@ -738,10 +738,10 @@ brw_reg_alloc::build_lane_offsets(const brw_builder &bld, uint32_t spill_offset, _mesa_set_add(spill_insts, inst); if (spill_offset > 0 && spill_offset <= 0xffffu) { - inst = ubld.MAD(offset, - brw_imm_uw(spill_offset), - retype(offset, BRW_TYPE_UW), - brw_imm_uw(4)); + inst = ubld.group(8, 0).MAD(offset, + brw_imm_uw(spill_offset), + retype(offset, BRW_TYPE_UW), + brw_imm_uw(4)); _mesa_set_add(spill_insts, inst); } else { /* Make the offset a dword */