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radeonsi: fix automatic DCC retiling after compute image stores

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Only internal compute shaders use DCC stores, so the TODOs are not
critical yet.

Fixes: 1d64a1045e - radeonsi: enable dcc image stores on gfx10+

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10261>
(cherry picked from commit a1653854f5)
This commit is contained in:
Marek Olšák 2021-04-14 20:08:03 -04:00 • committed by Eric Engestrom
parent 3a04f9ec5e
commit 7e8c906197
5 changed files with 23 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
.pick_status.json
View file

@ -85,7 +85,7 @@
"description": "radeonsi: fix automatic DCC retiling after compute image stores",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"master_sha": null,
"because_sha": "1d64a1045ea205ee0297d2f741a824811570fc6d"
},

12
src/gallium/drivers/radeonsi/si_compute.c
View file

@ -1004,6 +1004,18 @@ static void si_launch_grid(struct pipe_context *ctx, const struct pipe_grid_info
si_log_compute_state(sctx, sctx->log);
}
/* Mark displayable DCC as dirty for bound images. */
unsigned display_dcc_store_mask = sctx->images[PIPE_SHADER_COMPUTE].display_dcc_store_mask &
BITFIELD_MASK(program->sel.info.base.num_images);
while (display_dcc_store_mask) {
struct si_texture *tex = (struct si_texture *)
sctx->images[PIPE_SHADER_COMPUTE].views[u_bit_scan(&display_dcc_store_mask)].resource;
si_mark_display_dcc_dirty(sctx, tex);
}
/* TODO: Bindless images don't set displayable_dcc_dirty after image stores. */
sctx->compute_is_busy = true;
sctx->num_compute_calls++;

7
src/gallium/drivers/radeonsi/si_descriptors.c
View file

@ -686,6 +686,7 @@ static void si_disable_shader_image(struct si_context *ctx, unsigned shader, uns
memcpy(descs->list + desc_slot * 8, null_image_descriptor, 8 * 4);
images->enabled_mask &= ~(1u << slot);
images->display_dcc_store_mask &= ~(1u << slot);
ctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader);
}
}
@ -791,6 +792,7 @@ static void si_set_shader_image(struct si_context *ctx, unsigned shader, unsigne
if (res->b.b.target == PIPE_BUFFER || view->shader_access & SI_IMAGE_ACCESS_AS_BUFFER) {
images->needs_color_decompress_mask &= ~(1 << slot);
images->display_dcc_store_mask &= ~(1u << slot);
res->bind_history |= PIPE_BIND_SHADER_IMAGE;
} else {
struct si_texture *tex = (struct si_texture *)res;
@ -802,6 +804,11 @@ static void si_set_shader_image(struct si_context *ctx, unsigned shader, unsigne
images->needs_color_decompress_mask &= ~(1 << slot);
}
if (tex->surface.display_dcc_offset && view->access & PIPE_IMAGE_ACCESS_WRITE)
images->display_dcc_store_mask |= 1u << slot;
else
images->display_dcc_store_mask &= ~(1u << slot);
if (vi_dcc_enabled(tex, level) && p_atomic_read(&tex->framebuffers_bound))
ctx->need_check_render_feedback = true;
}

1
src/gallium/drivers/radeonsi/si_pipe.h
View file

@ -718,6 +718,7 @@ struct si_images {
struct pipe_image_view views[SI_NUM_IMAGES];
uint32_t needs_color_decompress_mask;
unsigned enabled_mask;
unsigned display_dcc_store_mask;
};
struct si_framebuffer {

2
src/gallium/drivers/radeonsi/si_state_draw.cpp
View file

@ -2200,6 +2200,8 @@ static void si_draw_vbo(struct pipe_context *ctx,
sctx->num_prim_restart_calls++;
}
/* TODO: Set displayable_dcc_dirty if image stores are used. */
DRAW_CLEANUP;
}