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radeonsi: fix automatic DCC retiling after DCC clear and DCC decompression

Browse source 
Fixes: d4f7962d48 - radeonsi: Add displayable DCC flushing without explicit flushes.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10261>
(cherry picked from commit 4d7dd094e3)
This commit is contained in:
Marek Olšák 2021-04-14 20:08:03 -04:00 • committed by Eric Engestrom
parent 742188d95a
commit 3a04f9ec5e
5 changed files with 23 additions and 24 deletions
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2
.pick_status.json
View file

@ -94,7 +94,7 @@
"description": "radeonsi: fix automatic DCC retiling after DCC clear and DCC decompression",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"master_sha": null,
"because_sha": "d4f7962d48b46d34319f75bba03fad22c30efdff"
},

1
src/gallium/drivers/radeonsi/si_blit.c
View file

@ -1374,6 +1374,7 @@ void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex)
si_clear_buffer(sctx, ptex, tex->surface.meta_offset,
tex->surface.meta_size, &clear_value, 4, SI_OP_SYNC_AFTER,
SI_COHERENCY_CB_META, SI_COMPUTE_CLEAR_METHOD);
si_mark_display_dcc_dirty(sctx, tex);
/* Clearing DCC metadata requires flushing L2 and invalidating L2 metadata to make
* the metadata visible to L2 caches. This is because clear_buffer uses plain stores

2
src/gallium/drivers/radeonsi/si_clear.c
View file

@ -667,7 +667,7 @@ static void si_fast_clear(struct si_context *sctx, unsigned *buffers,
clear_types |= SI_CLEAR_TYPE_DCC;
tex->separate_dcc_dirty = true;
tex->displayable_dcc_dirty = true;
si_mark_display_dcc_dirty(sctx, tex);
/* DCC fast clear with MSAA should clear CMASK to 0xC. */
if (tex->buffer.b.b.nr_samples >= 2 && tex->cmask_buffer) {

41
src/gallium/drivers/radeonsi/si_state.c
View file

@ -2600,32 +2600,29 @@ static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *sta
}
}
void si_mark_display_dcc_dirty(struct si_context *sctx, struct si_texture *tex)
{
if (!tex->surface.display_dcc_offset || tex->displayable_dcc_dirty)
return;
if (!(tex->buffer.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH)) {
struct hash_entry *entry = _mesa_hash_table_search(sctx->dirty_implicit_resources, tex);
if (!entry) {
struct pipe_resource *dummy = NULL;
pipe_resource_reference(&dummy, &tex->buffer.b.b);
_mesa_hash_table_insert(sctx->dirty_implicit_resources, tex, tex);
}
}
tex->displayable_dcc_dirty = true;
}
static void si_update_display_dcc_dirty(struct si_context *sctx)
{
const struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
struct si_surface *surf;
struct si_texture *tex;
int i;
for (i = 0; i < state->nr_cbufs; i++) {
if (!state->cbufs[i])
continue;
surf = (struct si_surface *)state->cbufs[i];
tex = (struct si_texture *)surf->base.texture;
if (!tex->surface.display_dcc_offset || tex->displayable_dcc_dirty)
continue;
if (!(tex->buffer.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH)) {
struct hash_entry *entry = _mesa_hash_table_search(sctx->dirty_implicit_resources, tex);
if (!entry) {
struct pipe_resource *dummy = NULL;
pipe_resource_reference(&dummy, &tex->buffer.b.b);
_mesa_hash_table_insert(sctx->dirty_implicit_resources, tex, tex);
}
}
tex->displayable_dcc_dirty = true;
for (unsigned i = 0; i < state->nr_cbufs; i++) {
if (state->cbufs[i])
si_mark_display_dcc_dirty(sctx, (struct si_texture *)state->cbufs[i]->texture);
}
}

1
src/gallium/drivers/radeonsi/si_state.h
View file

@ -540,6 +540,7 @@ struct pipe_sampler_view *si_create_sampler_view_custom(struct pipe_context *ctx
unsigned width0, unsigned height0,
unsigned force_level);
void si_update_fb_dirtiness_after_rendering(struct si_context *sctx);
void si_mark_display_dcc_dirty(struct si_context *sctx, struct si_texture *tex);
void si_update_ps_iter_samples(struct si_context *sctx);
void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st);
void si_restore_qbo_state(struct si_context *sctx, struct si_qbo_state *st);