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tu: Drop tu_cs_image_*_ref

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These were only used in one place.  Drop them and convert to using the
new register packers for improved cross-gen portability.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39029>
This commit is contained in:
Rob Clark 2025-12-17 13:03:45 -08:00 • committed by Marge Bot
parent 31d757495e
commit 7ce63372bd
2 changed files with 48 additions and 44 deletions
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68
src/freedreno/vulkan/tu_cmd_buffer.cc
View file

@ -671,17 +671,32 @@ tu6_emit_zs(struct tu_cmd_buffer *cmd,
&cmd->state.pass->attachments[a];
enum a6xx_depth_format fmt = tu6_pipe2depth(attachment->format);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
tu_cs_emit(cs, RB_DEPTH_BUFFER_INFO(CHIP,
.depth_format = fmt,
.tilemode = TILE6_3,
.losslesscompen = iview->view.ubwc_enabled,
).value);
if (attachment->format == VK_FORMAT_D32_SFLOAT_S8_UINT)
tu_cs_image_depth_ref(cs, iview, 0);
else
tu_cs_image_ref(cs, &iview->view, 0);
tu_cs_emit(cs, tu_attachment_gmem_offset(cmd, attachment, 0));
unsigned depth_pitch, depth_array_pitch;
uint64_t depth_base;
if (attachment->format == VK_FORMAT_D32_SFLOAT_S8_UINT) {
depth_pitch = iview->depth_pitch;
depth_array_pitch = iview->depth_layer_size;
depth_base = iview->depth_base_addr;
} else {
depth_pitch = iview->view.pitch;
depth_array_pitch = iview->view.layer_size;
depth_base = tu_layer_address(&iview->view, 0);
}
tu_cs_emit_regs(cs,
RB_DEPTH_BUFFER_INFO(CHIP,
.depth_format = fmt,
.tilemode = TILE6_3,
.losslesscompen = iview->view.ubwc_enabled,
),
A6XX_RB_DEPTH_BUFFER_PITCH(depth_pitch),
A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(depth_array_pitch),
A6XX_RB_DEPTH_BUFFER_BASE(depth_base),
A6XX_RB_DEPTH_GMEM_BASE(
tu_attachment_gmem_offset(cmd, attachment, 0)
),
);
tu_cs_emit_regs(cs, GRAS_SU_DEPTH_BUFFER_INFO(CHIP, .depth_format = fmt));
@ -691,18 +706,31 @@ tu6_emit_zs(struct tu_cmd_buffer *cmd,
if (attachment->format == VK_FORMAT_D32_SFLOAT_S8_UINT ||
attachment->format == VK_FORMAT_S8_UINT) {
tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_BUFFER_INFO, 6);
tu_cs_emit(cs, RB_STENCIL_BUFFER_INFO(CHIP,
.separate_stencil = true,
.tilemode = TILE6_3,
).value);
unsigned stencil_pitch, stencil_array_pitch, stencil_gmem_offset;
uint64_t stencil_base;
if (attachment->format == VK_FORMAT_D32_SFLOAT_S8_UINT) {
tu_cs_image_stencil_ref(cs, iview, 0);
tu_cs_emit(cs, tu_attachment_gmem_offset_stencil(cmd, attachment, 0));
stencil_pitch = iview->stencil_pitch;
stencil_array_pitch = iview->stencil_layer_size;
stencil_base = iview->stencil_base_addr;
stencil_gmem_offset = tu_attachment_gmem_offset_stencil(cmd, attachment, 0);
} else {
tu_cs_image_ref(cs, &iview->view, 0);
tu_cs_emit(cs, tu_attachment_gmem_offset(cmd, attachment, 0));
stencil_pitch = iview->view.pitch;
stencil_array_pitch = iview->view.layer_size;
stencil_base = tu_layer_address(&iview->view, 0);
stencil_gmem_offset = tu_attachment_gmem_offset(cmd, attachment, 0);
}
tu_cs_emit_regs(cs,
RB_STENCIL_BUFFER_INFO(CHIP,
.separate_stencil = true,
.tilemode = TILE6_3,
),
A6XX_RB_STENCIL_BUFFER_PITCH(stencil_pitch),
A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(stencil_array_pitch),
A6XX_RB_STENCIL_BUFFER_BASE(stencil_base),
A6XX_RB_STENCIL_GMEM_BASE(stencil_gmem_offset),
);
} else {
tu_cs_emit_regs(cs,
RB_STENCIL_BUFFER_INFO(CHIP, 0));

24
src/freedreno/vulkan/tu_image.cc
View file

@ -147,30 +147,6 @@ tu_layer_flag_address(const struct fdl6_view *iview, uint32_t layer)
return iview->ubwc_addr + iview->ubwc_layer_size * layer;
}
void
tu_cs_image_ref(struct tu_cs *cs, const struct fdl6_view *iview, uint32_t layer)
{
tu_cs_emit(cs, A6XX_RB_MRT_PITCH(0, iview->pitch).value);
tu_cs_emit(cs, iview->layer_size >> 6);
tu_cs_emit_qw(cs, tu_layer_address(iview, layer));
}
void
tu_cs_image_stencil_ref(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer)
{
tu_cs_emit(cs, A6XX_RB_STENCIL_BUFFER_PITCH(iview->stencil_pitch).value);
tu_cs_emit(cs, iview->stencil_layer_size >> 6);
tu_cs_emit_qw(cs, iview->stencil_base_addr + iview->stencil_layer_size * layer);
}
void
tu_cs_image_depth_ref(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer)
{
tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_PITCH(iview->depth_pitch).value);
tu_cs_emit(cs, iview->depth_layer_size >> 6);
tu_cs_emit_qw(cs, iview->depth_base_addr + iview->depth_layer_size * layer);
}
template <chip CHIP>
void
tu_cs_image_ref_2d(struct tu_cs *cs, const struct fdl6_view *iview, uint32_t layer, bool src)