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intel/xehp: Adjust TBIMR performance chicken bits.

Browse source 
This enables a couple of TBIMR performance tunables in
CHICKEN_RASTER_2 that default to disabled.  TBIMR fast clip appears to
help slightly with some geometry-bound workloads.  TBIMR open batch
allows the rasterizer to start working immediately on the first tile
of the framebuffer, even before the batch has been closed, which helps
reduce the latency cost of the tile walk.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25493>
This commit is contained in:
Francisco Jerez 2023-09-29 15:12:13 -07:00
parent 08fd259b5b
commit 7cdacaf493
3 changed files with 24 additions and 0 deletions
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9
src/gallium/drivers/iris/iris_state.c
View file

@ -1310,6 +1310,15 @@ iris_init_render_context(struct iris_batch *batch)
}
#endif
#if GFX_VERx10 == 125
iris_emit_reg(batch, GENX(CHICKEN_RASTER_2), reg) {
reg.TBIMROpenBatchEnable = true;
reg.TBIMRFastClip = true;
reg.TBIMROpenBatchEnableMask = true;
reg.TBIMRFastClipMask = true;
};
#endif
upload_pixel_hashing_tables(batch);
/* 3DSTATE_DRAWING_RECTANGLE is non-pipelined, so we want to avoid

6
src/intel/genxml/gen125.xml
View file

@ -2028,6 +2028,12 @@
<field name="AA Line Quality Fix" start="5" end="5" type="bool" />
<field name="AA Line Quality Fix Mask" start="21" end="21" type="bool" />
</register>
<register name="CHICKEN_RASTER_2" length="1" num="0x6208">
<field name="TBIMR Open Batch Enable" start="4" end="4" type="bool" />
<field name="TBIMR Fast Clip" start="5" end="5" type="bool" />
<field name="TBIMR Open Batch Enable Mask" start="20" end="20" type="bool" />
<field name="TBIMR Fast Clip Mask" start="21" end="21" type="bool" />
</register>
<register name="COMMON_SLICE_CHICKEN1" length="1" num="0x7010">
<field name="HIZ Plane Optimization disable bit" start="9" end="9" type="bool" />
<field name="HIZ Plane Optimization disable bit Mask" start="25" end="25" type="bool" />

9
src/intel/vulkan/genX_init_state.c
View file

@ -542,6 +542,15 @@ init_render_queue_state(struct anv_queue *queue, bool is_companion_rcs_batch)
}
#endif
#if GFX_VERx10 == 125
anv_batch_write_reg(&batch, GENX(CHICKEN_RASTER_2), reg) {
reg.TBIMROpenBatchEnable = true;
reg.TBIMRFastClip = true;
reg.TBIMROpenBatchEnableMask = true;
reg.TBIMRFastClipMask = true;
}
#endif
/* Set the "CONSTANT_BUFFER Address Offset Disable" bit, so
* 3DSTATE_CONSTANT_XS buffer 0 is an absolute address.
*