diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index c05324422de..70f08ae72c9 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -1310,6 +1310,15 @@ iris_init_render_context(struct iris_batch *batch)
}
#endif
+#if GFX_VERx10 == 125
+ iris_emit_reg(batch, GENX(CHICKEN_RASTER_2), reg) {
+ reg.TBIMROpenBatchEnable = true;
+ reg.TBIMRFastClip = true;
+ reg.TBIMROpenBatchEnableMask = true;
+ reg.TBIMRFastClipMask = true;
+ };
+#endif
+
upload_pixel_hashing_tables(batch);
/* 3DSTATE_DRAWING_RECTANGLE is non-pipelined, so we want to avoid
diff --git a/src/intel/genxml/gen125.xml b/src/intel/genxml/gen125.xml
index 106a8e5b407..4758086b928 100644
--- a/src/intel/genxml/gen125.xml
+++ b/src/intel/genxml/gen125.xml
@@ -2028,6 +2028,12 @@
+
+
+
+
+
+
diff --git a/src/intel/vulkan/genX_init_state.c b/src/intel/vulkan/genX_init_state.c
index 9fc5b1697de..caa4d1251a9 100644
--- a/src/intel/vulkan/genX_init_state.c
+++ b/src/intel/vulkan/genX_init_state.c
@@ -542,6 +542,15 @@ init_render_queue_state(struct anv_queue *queue, bool is_companion_rcs_batch)
}
#endif
+#if GFX_VERx10 == 125
+ anv_batch_write_reg(&batch, GENX(CHICKEN_RASTER_2), reg) {
+ reg.TBIMROpenBatchEnable = true;
+ reg.TBIMRFastClip = true;
+ reg.TBIMROpenBatchEnableMask = true;
+ reg.TBIMRFastClipMask = true;
+ }
+#endif
+
/* Set the "CONSTANT_BUFFER Address Offset Disable" bit, so
* 3DSTATE_CONSTANT_XS buffer 0 is an absolute address.
*