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Revert ABI breakage "amd: Add user queue HQD count to hw_ip info"

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This reverts commit 56d758d321.

It broke ABI between Mesa and libdrm, causing crashes due to stack smashing.

See: https://gitlab.freedesktop.org/mesa/libdrm/-/issues/121#note_3172362

Fixes: 56d758d321
(cherry picked from commit 5d92c92ce5)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38268>
This commit is contained in:
Marek Olšák 2025-11-01 22:20:47 -04:00 • committed by Dylan Baker
parent 90b6c3a8ac
commit 7c18540961
7 changed files with 4 additions and 19 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
.pick_status.json
View file

@ -474,7 +474,7 @@
"description": "Revert ABI breakage \"amd: Add user queue HQD count to hw_ip info\"",
"nominated": true,
"nomination_type": 2,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": "56d758d321fd87b883106585b564fac92aa0793a",
"notes": null

2
include/drm-uapi/amdgpu_drm.h
View file

@ -1489,8 +1489,6 @@ struct drm_amdgpu_info_hw_ip {
__u32 available_rings;
/** version info: bits 23:16 major, 15:8 minor, 7:0 revision */
__u32 ip_discovery_version;
/* Userq available slots */
__u32 userq_num_slots;
};
/* GFX metadata BO sizes and alignment info (in bytes) */

8
src/amd/common/ac_gpu_info.c
View file

@ -315,8 +315,6 @@ ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
info->ip[ip_type].num_queues = 1;
} else if (ip_info.available_rings) {
info->ip[ip_type].num_queues = util_bitcount(ip_info.available_rings);
} else if (ip_info.userq_num_slots) {
info->ip[ip_type].num_queue_slots = ip_info.userq_num_slots;
} else {
continue;
}
@ -1696,11 +1694,11 @@ void ac_print_gpu_info(const struct radeon_info *info, FILE *f)
fprintf(f, " clock_crystal_freq = %i KHz\n", info->clock_crystal_freq);
for (unsigned i = 0; i < AMD_NUM_IP_TYPES; i++) {
if (info->ip[i].num_queues || info->ip[i].num_queue_slots) {
fprintf(f, " IP %-7s %2u.%u \tqueues:%u \tqueue_slots:%u \talign:%u \tpad_dw:0x%x\n",
if (info->ip[i].num_queues) {
fprintf(f, " IP %-7s %2u.%u \tqueues:%u \talign:%u \tpad_dw:0x%x\n",
ac_get_ip_type_string(info, i),
info->ip[i].ver_major, info->ip[i].ver_minor, info->ip[i].num_queues,
info->ip[i].num_queue_slots,info->ip[i].ib_alignment, info->ip[i].ib_pad_dw_mask);
info->ip[i].ib_alignment, info->ip[i].ib_pad_dw_mask);
}
}

1
src/amd/common/ac_gpu_info.h
View file

@ -26,7 +26,6 @@ struct amd_ip_info {
uint8_t ver_minor;
uint8_t ver_rev;
uint8_t num_queues;
uint8_t num_queue_slots;
uint8_t num_instances;
uint32_t ib_alignment;
uint32_t ib_pad_dw_mask;

1
src/amd/common/ac_linux_drm.h
View file

@ -194,7 +194,6 @@ struct drm_amdgpu_info_hw_ip {
uint32_t ib_size_alignment;
uint32_t available_rings;
uint32_t ip_discovery_version;
uint32_t userq_num_slots;
};
struct drm_amdgpu_info_uq_fw_areas_gfx {

8
src/amd/drm-shim/amdgpu_devices.c
View file

@ -1329,7 +1329,6 @@ const struct amdgpu_device amdgpu_devices[] = {
.ib_size_alignment = 32,
.available_rings = 0x1,
.ip_discovery_version = 0xb0000,
.userq_num_slots = 2,
},
.hw_ip_compute = {
.hw_ip_version_major = 11,
@ -1339,7 +1338,6 @@ const struct amdgpu_device amdgpu_devices[] = {
.ib_size_alignment = 32,
.available_rings = 0xf,
.ip_discovery_version = 0xb0000,
.userq_num_slots = 16,
},
.fw_gfx_me = {
.ver = 1486,
@ -1460,7 +1458,6 @@ const struct amdgpu_device amdgpu_devices[] = {
.ib_size_alignment = 32,
.available_rings = 0x1,
.ip_discovery_version = 0xb0002,
.userq_num_slots = 0x0,
},
.hw_ip_compute = {
.hw_ip_version_major = 11,
@ -1470,7 +1467,6 @@ const struct amdgpu_device amdgpu_devices[] = {
.ib_size_alignment = 32,
.available_rings = 0xf,
.ip_discovery_version = 0xb0002,
.userq_num_slots = 0x0,
},
.fw_gfx_me = {
.ver = 2390,
@ -2070,7 +2066,6 @@ const struct amdgpu_device amdgpu_devices[] = {
.ib_size_alignment = 32,
.available_rings = 0x1,
.ip_discovery_version = 0xb0500,
.userq_num_slots = 2,
},
.hw_ip_compute = {
.hw_ip_version_major = 11,
@ -2080,7 +2075,6 @@ const struct amdgpu_device amdgpu_devices[] = {
.ib_size_alignment = 32,
.available_rings = 0xf,
.ip_discovery_version = 0xb0500,
.userq_num_slots = 16,
},
.fw_gfx_me = {
.ver = 29,
@ -2201,7 +2195,6 @@ const struct amdgpu_device amdgpu_devices[] = {
.ib_size_alignment = 32,
.available_rings = 0x1,
.ip_discovery_version = 0xc0001,
.userq_num_slots = 8,
},
.hw_ip_compute = {
.hw_ip_version_major = 12,
@ -2211,7 +2204,6 @@ const struct amdgpu_device amdgpu_devices[] = {
.ib_size_alignment = 32,
.available_rings = 0xf,
.ip_discovery_version = 0xc0001,
.userq_num_slots = 8,
},
.fw_gfx_me = {
.ver = 2590,

1
src/amd/drm-shim/amdgpu_dump_states.c
View file

@ -379,7 +379,6 @@ amdgpu_dump_hw_ips(int fd)
printf(" .ib_size_alignment = %u,\n", info.ib_size_alignment);
printf(" .available_rings = 0x%x,\n", info.available_rings);
printf(" .ip_discovery_version = 0x%04x,\n", info.ip_discovery_version);
printf(" .userq_num_slots = 0x%x,\n", info.userq_num_slots);
printf("},\n");
}
}