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brw: Add latencies for HDC/RC memory fences

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We're about to start lowering these in the IR, at which point the
scheduler will see SEND instructions with fence messages.  Previously,
we handled those in the generator, and didn't handle the virtual opcodes
here, letting them fall through to the default case of 14 cycles.

These new numbers are completely fabricated, matching the times we have
for atomic operations.  This is basically what we did for LSC atomics.
While it may not be accurate, it's at least better than 14 cycles.

Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33297>
This commit is contained in:
Kenneth Graunke 2025-01-27 16:22:05 -08:00 • committed by Marge Bot
parent b9de19f917
commit 7b4e31b243
1 changed files with 5 additions and 0 deletions
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5
src/intel/compiler/brw_schedule_instructions.cpp
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@ -371,6 +371,7 @@ schedule_node::set_latency(const struct brw_isa_info *isa)
break;
case GFX7_DATAPORT_RC_TYPED_ATOMIC_OP:
case GFX7_DATAPORT_RC_MEMORY_FENCE:
/* See also SHADER_OPCODE_TYPED_ATOMIC */
latency = 14000;
break;
@ -448,6 +449,10 @@ schedule_node::set_latency(const struct brw_isa_info *isa)
latency = 14000;
break;
case GFX7_DATAPORT_DC_MEMORY_FENCE:
latency = 14000;
break;
default:
unreachable("Unknown data cache message");
}