From 7b4e31b2439e85c66adce52d97c942a34ce57b74 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Mon, 27 Jan 2025 16:22:05 -0800 Subject: [PATCH] brw: Add latencies for HDC/RC memory fences We're about to start lowering these in the IR, at which point the scheduler will see SEND instructions with fence messages. Previously, we handled those in the generator, and didn't handle the virtual opcodes here, letting them fall through to the default case of 14 cycles. These new numbers are completely fabricated, matching the times we have for atomic operations. This is basically what we did for LSC atomics. While it may not be accurate, it's at least better than 14 cycles. Acked-by: Caio Oliveira Reviewed-by: Lionel Landwerlin Part-of: --- src/intel/compiler/brw_schedule_instructions.cpp | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/intel/compiler/brw_schedule_instructions.cpp b/src/intel/compiler/brw_schedule_instructions.cpp index f7f192c58dd..15efacc507d 100644 --- a/src/intel/compiler/brw_schedule_instructions.cpp +++ b/src/intel/compiler/brw_schedule_instructions.cpp @@ -371,6 +371,7 @@ schedule_node::set_latency(const struct brw_isa_info *isa) break; case GFX7_DATAPORT_RC_TYPED_ATOMIC_OP: + case GFX7_DATAPORT_RC_MEMORY_FENCE: /* See also SHADER_OPCODE_TYPED_ATOMIC */ latency = 14000; break; @@ -448,6 +449,10 @@ schedule_node::set_latency(const struct brw_isa_info *isa) latency = 14000; break; + case GFX7_DATAPORT_DC_MEMORY_FENCE: + latency = 14000; + break; + default: unreachable("Unknown data cache message"); }