diff --git a/src/gallium/drivers/iris/iris_program.c b/src/gallium/drivers/iris/iris_program.c
index 7f627f9ff61..a48fc3a685b 100644
--- a/src/gallium/drivers/iris/iris_program.c
+++ b/src/gallium/drivers/iris/iris_program.c
@@ -2690,7 +2690,6 @@ iris_compile_fs(struct iris_screen *screen,
    brw_nir_lower_fs_outputs(nir);
 
    int null_rts = brw_nir_fs_needs_null_rt(devinfo, nir,
-                                           key->multisample_fbo,
                                            key->alpha_to_coverage) ? 1 : 0;
 
    struct iris_binding_table bt;
diff --git a/src/intel/compiler/brw_nir.h b/src/intel/compiler/brw_nir.h
index 1cde9be3eae..f9dc7dce621 100644
--- a/src/intel/compiler/brw_nir.h
+++ b/src/intel/compiler/brw_nir.h
@@ -143,8 +143,7 @@ brw_nir_ubo_surface_index_get_bti(nir_src src)
 /* Returns true if a fragment shader needs at least one render target */
 static inline bool
 brw_nir_fs_needs_null_rt(const struct intel_device_info *devinfo,
-                         nir_shader *nir,
-                         bool multisample_fbo, bool alpha_to_coverage)
+                         nir_shader *nir, bool alpha_to_coverage)
 {
    assert(nir->info.stage == MESA_SHADER_FRAGMENT);
 
@@ -158,15 +157,11 @@ brw_nir_fs_needs_null_rt(const struct intel_device_info *devinfo,
     * output.
     */
    if (nir->info.outputs_written & (BITFIELD_BIT(FRAG_RESULT_DEPTH) |
-                                    BITFIELD_BIT(FRAG_RESULT_STENCIL)))
+                                    BITFIELD_BIT(FRAG_RESULT_STENCIL) |
+                                    BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK)))
       return true;
 
-   uint64_t relevant_outputs = 0;
-   if (multisample_fbo)
-      relevant_outputs |= BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK);
-
-   return (alpha_to_coverage ||
-           (nir->info.outputs_written & relevant_outputs) != 0);
+   return alpha_to_coverage;
 }
 
 void brw_preprocess_nir(const struct brw_compiler *compiler,
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index f65e06ef682..0bbcc67e395 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -1522,7 +1522,6 @@ anv_pipeline_link_fs(const struct brw_compiler *compiler,
       num_rt_bindings = stage->key.wm.nr_color_regions;
    } else if (brw_nir_fs_needs_null_rt(
                  compiler->devinfo, stage->nir,
-                 stage->key.wm.multisample_fbo != INTEL_NEVER,
                  stage->key.wm.alpha_to_coverage != INTEL_NEVER)) {
       /* Ensure the shader doesn't discard the writes */
       stage->key.wm.color_outputs_valid = 0x1;