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https://gitlab.freedesktop.org/mesa/mesa.git
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amd: improve the IB parser, parse more packets
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23687>
This commit is contained in:
Marek Olšák
Marge Bot
parent
95a85d1b37
commit
789a3b24c1
4 changed files with 117 additions and 36 deletions
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@ -35,12 +35,14 @@ DEBUG_GET_ONCE_BOOL_OPTION(color, "AMD_COLOR", true);
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#define COLOR_GREEN "\033[1;32m"
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#define COLOR_YELLOW "\033[1;33m"
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#define COLOR_CYAN "\033[1;36m"
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#define COLOR_PURPLE "\033[1;35m"
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#define O_COLOR_RESET (debug_get_option_color() ? COLOR_RESET : "")
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#define O_COLOR_RED (debug_get_option_color() ? COLOR_RED : "")
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#define O_COLOR_GREEN (debug_get_option_color() ? COLOR_GREEN : "")
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#define O_COLOR_YELLOW (debug_get_option_color() ? COLOR_YELLOW : "")
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#define O_COLOR_CYAN (debug_get_option_color() ? COLOR_CYAN : "")
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#define O_COLOR_PURPLE (debug_get_option_color() ? COLOR_PURPLE : "")
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#define INDENT_PKT 8
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@ -84,6 +86,12 @@ static void print_value(FILE *file, uint32_t value, int bits)
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}
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}
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static void print_reserved_dword(FILE *file, uint32_t value)
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{
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print_spaces(file, INDENT_PKT);
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fprintf(file, "(reserved)\n");
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}
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static void print_named_value(FILE *file, const char *name, uint32_t value, int bits)
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{
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print_spaces(file, INDENT_PKT);
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@ -93,6 +101,15 @@ static void print_named_value(FILE *file, const char *name, uint32_t value, int
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print_value(file, value, bits);
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}
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static void print_string_value(FILE *file, const char *name, const char *value)
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{
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print_spaces(file, INDENT_PKT);
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fprintf(file, "%s%s%s <- ",
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O_COLOR_YELLOW, name,
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O_COLOR_RESET);
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fprintf(file, "%s\n", value);
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}
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static const struct si_reg *find_register(enum amd_gfx_level gfx_level, enum radeon_family family,
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unsigned offset)
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{
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@ -242,39 +259,65 @@ static void ac_parse_set_reg_packet(FILE *f, unsigned count, unsigned reg_offset
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unsigned index = reg_dw >> 28;
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int i;
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if (index != 0) {
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print_spaces(f, INDENT_PKT);
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fprintf(f, "INDEX = %u\n", index);
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}
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if (index != 0)
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print_named_value(f, "INDEX", index, 32);
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for (i = 0; i < count; i++)
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ac_dump_reg(f, ib->gfx_level, ib->family, reg + i * 4, ac_ib_get(ib), ~0);
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}
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static void ac_parse_set_reg_pairs_packed_packet(FILE *f, unsigned count, unsigned reg_base,
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struct ac_ib_parser *ib)
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{
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unsigned reg_offset0 = 0, reg_offset1 = 0;
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print_named_value(f, "REG_COUNT", ac_ib_get(ib), 32);
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for (unsigned i = 0; i < count; i++) {
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if (i % 3 == 0) {
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unsigned tmp = ac_ib_get(ib);
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reg_offset0 = ((tmp & 0xffff) << 2) + reg_base;
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reg_offset1 = ((tmp >> 16) << 2) + reg_base;
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} else if (i % 3 == 1) {
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ac_dump_reg(f, ib->gfx_level, ib->family, reg_offset0, ac_ib_get(ib), ~0);
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} else {
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ac_dump_reg(f, ib->gfx_level, ib->family, reg_offset1, ac_ib_get(ib), ~0);
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}
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}
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}
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static void ac_parse_packet3(FILE *f, uint32_t header, struct ac_ib_parser *ib,
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int *current_trace_id)
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{
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unsigned first_dw = ib->cur_dw;
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int count = PKT_COUNT_G(header);
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unsigned op = PKT3_IT_OPCODE_G(header);
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const char *predicate = PKT3_PREDICATE(header) ? "(predicate)" : "";
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const char *shader_type = PKT3_SHADER_TYPE_G(header) ? "(shader_type=compute)" : "";
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const char *predicated = PKT3_PREDICATE(header) ? "(predicated)" : "";
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const char *reset_filter_cam = PKT3_RESET_FILTER_CAM_G(header) ? "(reset_filter_cam)" : "";
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int i;
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unsigned tmp;
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/* Print the name first. */
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for (i = 0; i < ARRAY_SIZE(packet3_table); i++)
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if (packet3_table[i].op == op)
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break;
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if (i < ARRAY_SIZE(packet3_table)) {
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const char *name = sid_strings + packet3_table[i].name_offset;
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const char *pkt_name = i < ARRAY_SIZE(packet3_table) ? sid_strings + packet3_table[i].name_offset
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: "UNKNOWN";
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const char *color;
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if (op == PKT3_SET_CONTEXT_REG || op == PKT3_SET_CONFIG_REG || op == PKT3_SET_UCONFIG_REG ||
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op == PKT3_SET_UCONFIG_REG_INDEX || op == PKT3_SET_SH_REG || op == PKT3_SET_SH_REG_INDEX)
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fprintf(f, "%s%s%s%s:\n", O_COLOR_CYAN, name, predicate, O_COLOR_RESET);
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else
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fprintf(f, "%s%s%s%s:\n", O_COLOR_GREEN, name, predicate, O_COLOR_RESET);
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} else
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fprintf(f, "%sPKT3_UNKNOWN 0x%x%s%s:\n", O_COLOR_RED, op, predicate, O_COLOR_RESET);
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if (strstr(pkt_name, "DRAW") || strstr(pkt_name, "DISPATCH"))
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color = O_COLOR_PURPLE;
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else if (strstr(pkt_name, "SET") == pkt_name && strstr(pkt_name, "REG"))
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color = O_COLOR_CYAN;
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else if (i >= ARRAY_SIZE(packet3_table))
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color = O_COLOR_RED;
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else
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color = O_COLOR_GREEN;
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fprintf(f, "%s%s%s%s%s%s:\n", color, pkt_name, O_COLOR_RESET,
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shader_type, predicated, reset_filter_cam);
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/* Print the contents. */
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switch (op) {
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@ -292,25 +335,44 @@ static void ac_parse_packet3(FILE *f, uint32_t header, struct ac_ib_parser *ib,
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case PKT3_SET_SH_REG_INDEX:
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ac_parse_set_reg_packet(f, count, SI_SH_REG_OFFSET, ib);
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break;
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case PKT3_SET_CONTEXT_REG_PAIRS_PACKED:
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ac_parse_set_reg_pairs_packed_packet(f, count, SI_CONTEXT_REG_OFFSET, ib);
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break;
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case PKT3_SET_SH_REG_PAIRS_PACKED:
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case PKT3_SET_SH_REG_PAIRS_PACKED_N:
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ac_parse_set_reg_pairs_packed_packet(f, count, SI_SH_REG_OFFSET, ib);
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break;
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case PKT3_ACQUIRE_MEM:
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if (ib->gfx_level >= GFX11 && G_585_PWS_ENA(ib->ib[ib->cur_dw + 5])) {
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ac_dump_reg(f, ib->gfx_level, ib->family, R_580_ACQUIRE_MEM_PWS_2, ac_ib_get(ib), ~0);
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print_named_value(f, "GCR_SIZE", ac_ib_get(ib), 32);
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print_named_value(f, "GCR_SIZE_HI", ac_ib_get(ib), 25);
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print_named_value(f, "GCR_BASE_LO", ac_ib_get(ib), 32);
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print_named_value(f, "GCR_BASE_HI", ac_ib_get(ib), 32);
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ac_dump_reg(f, ib->gfx_level, ib->family, R_585_ACQUIRE_MEM_PWS_7, ac_ib_get(ib), ~0);
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ac_dump_reg(f, ib->gfx_level, ib->family, R_586_GCR_CNTL, ac_ib_get(ib), ~0);
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break;
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if (ib->gfx_level >= GFX11) {
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if (G_585_PWS_ENA(ib->ib[ib->cur_dw + 5])) {
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ac_dump_reg(f, ib->gfx_level, ib->family, R_580_ACQUIRE_MEM_PWS_2, ac_ib_get(ib), ~0);
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print_named_value(f, "GCR_SIZE", ac_ib_get(ib), 32);
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print_named_value(f, "GCR_SIZE_HI", ac_ib_get(ib), 25);
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print_named_value(f, "GCR_BASE_LO", ac_ib_get(ib), 32);
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print_named_value(f, "GCR_BASE_HI", ac_ib_get(ib), 32);
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ac_dump_reg(f, ib->gfx_level, ib->family, R_585_ACQUIRE_MEM_PWS_7, ac_ib_get(ib), ~0);
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ac_dump_reg(f, ib->gfx_level, ib->family, R_586_GCR_CNTL, ac_ib_get(ib), ~0);
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} else {
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print_string_value(f, "ENGINE_SEL", ac_ib_get(ib) & 0x80000000 ? "ME" : "PFP");
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print_named_value(f, "GCR_SIZE", ac_ib_get(ib), 32);
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print_named_value(f, "GCR_SIZE_HI", ac_ib_get(ib), 25);
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print_named_value(f, "GCR_BASE_LO", ac_ib_get(ib), 32);
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print_named_value(f, "GCR_BASE_HI", ac_ib_get(ib), 32);
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print_named_value(f, "POLL_INTERVAL", ac_ib_get(ib), 16);
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ac_dump_reg(f, ib->gfx_level, ib->family, R_586_GCR_CNTL, ac_ib_get(ib), ~0);
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}
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} else {
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tmp = ac_ib_get(ib);
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ac_dump_reg(f, ib->gfx_level, ib->family, R_0301F0_CP_COHER_CNTL, tmp, 0x7fffffff);
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print_string_value(f, "ENGINE_SEL", tmp & 0x80000000 ? "ME" : "PFP");
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ac_dump_reg(f, ib->gfx_level, ib->family, R_0301F4_CP_COHER_SIZE, ac_ib_get(ib), ~0);
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ac_dump_reg(f, ib->gfx_level, ib->family, R_030230_CP_COHER_SIZE_HI, ac_ib_get(ib), ~0);
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ac_dump_reg(f, ib->gfx_level, ib->family, R_0301F8_CP_COHER_BASE, ac_ib_get(ib), ~0);
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ac_dump_reg(f, ib->gfx_level, ib->family, R_0301E4_CP_COHER_BASE_HI, ac_ib_get(ib), ~0);
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print_named_value(f, "POLL_INTERVAL", ac_ib_get(ib), 16);
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if (ib->gfx_level >= GFX10)
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ac_dump_reg(f, ib->gfx_level, ib->family, R_586_GCR_CNTL, ac_ib_get(ib), ~0);
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}
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ac_dump_reg(f, ib->gfx_level, ib->family, R_0301F0_CP_COHER_CNTL, ac_ib_get(ib), ~0);
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ac_dump_reg(f, ib->gfx_level, ib->family, R_0301F4_CP_COHER_SIZE, ac_ib_get(ib), ~0);
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ac_dump_reg(f, ib->gfx_level, ib->family, R_030230_CP_COHER_SIZE_HI, ac_ib_get(ib), ~0);
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ac_dump_reg(f, ib->gfx_level, ib->family, R_0301F8_CP_COHER_BASE, ac_ib_get(ib), ~0);
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ac_dump_reg(f, ib->gfx_level, ib->family, R_0301E4_CP_COHER_BASE_HI, ac_ib_get(ib), ~0);
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print_named_value(f, "POLL_INTERVAL", ac_ib_get(ib), 16);
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if (ib->gfx_level >= GFX10)
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ac_dump_reg(f, ib->gfx_level, ib->family, R_586_GCR_CNTL, ac_ib_get(ib), ~0);
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break;
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case PKT3_SURFACE_SYNC:
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if (ib->gfx_level >= GFX7) {
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@ -477,6 +539,7 @@ static void ac_parse_packet3(FILE *f, uint32_t header, struct ac_ib_parser *ib,
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case PKT3_CLEAR_STATE:
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case PKT3_INCREMENT_DE_COUNTER:
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case PKT3_PFP_SYNC_ME:
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print_reserved_dword(f, ac_ib_get(ib));
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break;
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case PKT3_NOP:
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if (header == PKT3_NOP_PAD) {
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@ -512,6 +575,22 @@ static void ac_parse_packet3(FILE *f, uint32_t header, struct ac_ib_parser *ib,
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break;
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}
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break;
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case PKT3_DISPATCH_DIRECT:
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ac_dump_reg(f, ib->gfx_level, ib->family, R_00B804_COMPUTE_DIM_X, ac_ib_get(ib), ~0);
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ac_dump_reg(f, ib->gfx_level, ib->family, R_00B808_COMPUTE_DIM_Y, ac_ib_get(ib), ~0);
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ac_dump_reg(f, ib->gfx_level, ib->family, R_00B80C_COMPUTE_DIM_Z, ac_ib_get(ib), ~0);
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ac_dump_reg(f, ib->gfx_level, ib->family, R_00B800_COMPUTE_DISPATCH_INITIATOR,
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ac_ib_get(ib), ~0);
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break;
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case PKT3_DISPATCH_INDIRECT:
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print_named_value(f, "DATA_OFFSET", ac_ib_get(ib), 32);
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ac_dump_reg(f, ib->gfx_level, ib->family, R_00B800_COMPUTE_DISPATCH_INITIATOR,
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ac_ib_get(ib), ~0);
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break;
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case PKT3_SET_BASE:
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tmp = ac_ib_get(ib);
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print_string_value(f, "BASE_INDEX", tmp == 1 ? "INDIRECT_BASE" : COLOR_RED "UNKNOWN" COLOR_RESET);
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break;
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}
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/* print additional dwords */
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@ -293,8 +293,10 @@
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#define PKT3_IT_OPCODE_G(x) (((x) >> 8) & 0xFF)
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#define PKT3_IT_OPCODE_C 0xFFFF00FF
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#define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
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#define PKT3_SHADER_TYPE_S(x) (((unsigned)(x)&0x1) << 1)
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#define PKT3_RESET_FILTER_CAM(x) (((unsigned)(x)&0x1) << 2)
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#define PKT3_SHADER_TYPE_S(x) (((unsigned)(x) & 0x1) << 1)
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#define PKT3_SHADER_TYPE_G(x) (((x) >> 1) & 0x1)
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#define PKT3_RESET_FILTER_CAM_S(x) (((unsigned)(x) & 0x1) << 2)
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#define PKT3_RESET_FILTER_CAM_G(x) (((unsigned)(x) >> 2) & 0x1)
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#define PKT3(op, count, predicate) \
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(PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
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@ -7936,7 +7936,7 @@ radv_cs_emit_indirect_mesh_draw_packet(struct radv_cmd_buffer *cmd_buffer, uint3
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uint32_t xyz_dim_enable = 1; /* TODO: disable XYZ_DIM when unneeded */
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uint32_t mode1_enable = 1; /* legacy fast launch mode */
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radeon_emit(cs, PKT3(PKT3_DISPATCH_MESH_INDIRECT_MULTI, 7, predicating) | PKT3_RESET_FILTER_CAM(1));
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radeon_emit(cs, PKT3(PKT3_DISPATCH_MESH_INDIRECT_MULTI, 7, predicating) | PKT3_RESET_FILTER_CAM_S(1));
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radeon_emit(cs, 0); /* data_offset */
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radeon_emit(cs, S_4C1_XYZ_DIM_REG(xyz_dim_reg) | S_4C1_DRAW_INDEX_REG(draw_id_reg));
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if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX11)
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@ -8036,7 +8036,7 @@ radv_cs_emit_dispatch_taskmesh_gfx_packet(struct radv_cmd_buffer *cmd_buffer)
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uint32_t mode1_en = 1; /* legacy fast launch mode */
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uint32_t linear_dispatch_en = cmd_buffer->state.shaders[MESA_SHADER_TASK]->info.cs.linear_taskmesh_dispatch;
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radeon_emit(cs, PKT3(PKT3_DISPATCH_TASKMESH_GFX, 2, predicating) | PKT3_RESET_FILTER_CAM(1));
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radeon_emit(cs, PKT3(PKT3_DISPATCH_TASKMESH_GFX, 2, predicating) | PKT3_RESET_FILTER_CAM_S(1));
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radeon_emit(cs, S_4D0_RING_ENTRY_REG(ring_entry_reg) | S_4D0_XYZ_DIM_REG(xyz_dim_reg));
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if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX11)
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radeon_emit(cs, S_4D1_XYZ_DIM_ENABLE(xyz_dim_en) | S_4D1_MODE1_ENABLE(mode1_en) |
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@ -179,7 +179,7 @@ radeon_set_perfctr_reg(struct radv_cmd_buffer *cmd_buffer, unsigned reg, unsigne
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bool filter_cam_workaround =
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cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX10 && cmd_buffer->qf == RADV_QUEUE_GENERAL;
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radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, 1, 0) | PKT3_RESET_FILTER_CAM(filter_cam_workaround));
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radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, 1, 0) | PKT3_RESET_FILTER_CAM_S(filter_cam_workaround));
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radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);
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radeon_emit(cs, value);
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}
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